 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| D at a S h e e t , D S 2 .1 , J u l y 2 00 3 DELIC-LC DELIC-PB DSP Embedded Line and Port Interface Controller PEB 20570 Version 3.1 PEB 20571 Version 3.1 Wire d Communications Never stop thinking. Edition 2003-07-31 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 8/4/03. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D at a S h e e t , D S 2 .1 , J u l y 2 00 3 DELIC-LC DELIC-PB DSP Embedded Line and Port Interface Controller PEB 20570 Version 3.1 PEB 20571 Version 3.1 Wire d Communications Never stop thinking. PEB 20570 Revision History: Previous Version: Page 2003-07-31 DS2 DS 2.1 Subjects (major changes since last revision) Trademarks updated For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com Note: OCEM(R) and OakDSPCore(R) (OAK(R)) are registered trademarks of ParthusCeva, Inc.. PEB 20570 PEB 20571 Table of Contents 1 1.1 1.2 1.3 1.4 1.4.1 1.4.2 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.2.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.4 3.2.4.1 3.2.4.2 3.3 3.3.1 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.5.1 3.5.2 4 4.1 4.2 4.2.1 4.2.2 Data Sheet Page 2 4 4 6 7 7 8 10 10 11 12 24 38 40 40 41 41 42 42 45 48 48 50 54 55 58 63 63 64 64 64 66 66 67 67 67 69 70 71 71 71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELIC-LC Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELIC-PB Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications for DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications for DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions for DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions for DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . Strap Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2000 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2000 Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command and Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UPN State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INFO Structure on the UPN Interface . . . . . . . . . . . . . . . . . . . . . . . . UPN Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/T State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals / Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel/Infineon or Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . De-Multiplexed or Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA or Non-DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELIC External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2000 Transceiver Unit (TRANSIU) . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2000 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2000 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2003-07-31 PEB 20570 PEB 20571 Table of Contents Page 4.2.3 Initialization of the VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.4 IOM-2000 Command and Status Interface . . . . . . . . . . . . . . . . . . . . . . 72 4.2.4.1 Initialization Mode Command Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.4.2 Operational Mode Command/Status Bits . . . . . . . . . . . . . . . . . . . . . 72 4.2.4.3 Command/Status Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.4.4 Command and Status format in the Data RAM . . . . . . . . . . . . . . . . . 74 4.2.5 UPN Mode Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.2.6 UPN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.2.7 UPN Framing Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.7.1 Framing Bit (LF-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.7.2 Multiframing Bit (M-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.7.3 DC-Balancing Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.2.7.4 UPN Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.2.7.5 UPN Scrambler/Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2.8 DECT Synchronization for UPN- Interface . . . . . . . . . . . . . . . . . . . . . . 82 4.2.9 S/T Interface Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2.9.1 LT-S mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.2.9.2 LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.10 S/T Mode Control and Framing Bits on IOM-2000 . . . . . . . . . . . . . . . . 90 4.2.10.1 Framing Bit (F-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.2.10.2 Multiframing Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.2.10.3 Fa/N Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.10.4 DC-Balancing Bit (L-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.11 IOM-2000 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.11.1 S/T Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.12 Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3 IOM-2 Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.1 IOMU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.2 IOMU Functional and Operational Description . . . . . . . . . . . . . . . . . . . 96 4.3.2.1 Frame-Wise Buffer Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.3.2.2 DSP Inaccessible Buffer (I-buffer) Logical Structure . . . . . . . . . . . . . 96 4.3.2.3 DSP Access to the D-Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.3.2.4 Circular Buffer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.3.2.5 IOM-2 Interface Data Rate Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.3.2.6 IOMU Serial Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.3.2.7 IOMU Parallel Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.3.2.8 IOM-2 Push-Pull and Open-Drain Modes . . . . . . . . . . . . . . . . . . . . 102 4.3.2.9 Support of DRDY Signal from QUAT-S . . . . . . . . . . . . . . . . . . . . . . 103 4.4 PCM Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.4.1 PCMU Functional and Operational Description . . . . . . . . . . . . . . . . . . 105 4.4.1.1 Frame-Wise Buffer Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.4.1.2 DSP Inaccessible Buffer (I-buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Data Sheet 2003-07-31 PEB 20570 PEB 20571 Table of Contents 4.4.1.3 4.4.1.4 4.4.1.5 4.4.1.6 4.4.1.7 4.5 4.6 4.6.1 4.6.2 4.6.2.1 4.6.2.2 4.6.2.3 4.6.2.4 4.6.2.5 4.6.3 4.7 4.7.1 4.7.2 4.7.3 4.7.3.1 4.7.3.2 4.7.4 4.7.5 4.7.6 4.7.6.1 4.7.7 4.7.8 4.7.9 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 4.9 4.9.1 4.9.2 4.9.3 4.10 4.10.1 Data Sheet Page 106 107 108 108 109 111 113 113 115 115 115 116 116 116 116 119 119 119 120 120 120 122 124 124 124 125 125 126 127 127 127 127 128 129 129 130 131 131 131 132 133 136 DSP Accessible Buffer (D-Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . PCMU Interface Data Rate Modes . . . . . . . . . . . . . . . . . . . . . . . . . PCMU Serial Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMU Parallel Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMU Tri-state Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-/-law Conversion Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLCU Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization of the HDLCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting a Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ending a Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aborting a Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Access to the HDLCU Buffers . . . . . . . . . . . . . . . . . . . . . . . . . Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC General Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . External Configuration and Handshaking in Bus Mode . . . . . . . . . . . . External Tri-State in Point-to-Multi-Point Mode . . . . . . . . . . . . . . . . Arbitration Between Several GHDLCs . . . . . . . . . . . . . . . . . . . . . . . GHDLC Memory Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Protocol Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC possible Data Rates for the DELIC-LC/PB . . . . . . . . . . . . . . . GHDLC Using external DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . DSP Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Run Time Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Bus and Program Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . Boot Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Execution and Boot Strap Pin Setting . . . . . . . . . . . . . . . . . . . . General Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OAK Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Mailbox (DELIC-PB only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2003-07-31 PEB 20570 PEB 20571 Table of Contents Page 137 137 137 137 139 141 142 142 144 144 144 144 145 145 145 146 146 146 146 147 150 151 151 161 161 161 162 164 167 168 173 174 175 176 177 177 178 179 181 182 183 4.10.1.1 Two-cycle DMA Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.1.2 Fly-by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.2 PEC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.3 Transmit DMA Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.4 Receive DMA Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.5 FIFO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.2 DSP Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.3 PCM Master/Slave Mode Clocks Selection . . . . . . . . . . . . . . . . . . . . . 4.11.4 DELIC Clock System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.5 IOM-2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.6 IOM-2000 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.7 REFCLK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.8 GHDLC Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1 5.1.1 5.1.2 5.1.3 5.2 6 6.1 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 6.2.1.6 6.2.1.7 6.2.1.8 6.2.1.9 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.2.2.4 6.2.2.5 6.2.3 Data Sheet DELIC Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Register Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Program Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Data Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSIU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSIU IOM-2000 Configuration Register . . . . . . . . . . . . . . . . . . TRANSIU Channel Configuration Registers . . . . . . . . . . . . . . . . . . VIP Command Registers (VIPCMR0, VIPCMR1, VIPCMR2) . . . . . VIP Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSIU Initialization Channel Command Register . . . . . . . . . . . . TRANSIU Initialization Channel Status Register (TICSTR) . . . . . . . Up Test Loop Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambler Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambler Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOMU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOMU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOMU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOMU Tri-State Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . IOMU DRDY Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOMU Data Prefix Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2003-07-31 PEB 20570 PEB 20571 Table of Contents 6.2.3.1 6.2.3.2 6.2.3.3 6.2.3.4 6.2.4 6.2.4.1 6.2.4.2 6.2.4.3 6.2.5 6.2.5.1 6.2.5.2 6.2.5.3 6.2.5.4 6.2.6 6.2.6.1 6.2.6.2 6.2.6.3 6.2.6.4 6.2.6.5 6.2.6.6 6.2.6.7 6.2.6.8 6.2.6.9 6.2.6.10 6.2.6.11 6.2.6.12 6.2.6.13 6.2.6.14 6.2.6.15 6.2.7 6.2.7.1 6.2.7.2 6.2.7.3 6.2.7.4 6.2.8 6.2.8.1 6.2.8.2 6.2.9 6.2.9.1 6.2.9.2 6.2.9.3 6.2.9.4 Data Sheet Page 183 184 185 187 188 188 189 190 191 191 192 193 195 197 197 198 199 200 201 203 204 206 207 208 209 210 211 212 213 214 214 215 216 217 218 218 220 221 221 222 223 224 PCMU Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMU Tri-state Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . PCMU Data Prefix Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-/-law Unit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/-law Unit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/-law Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/-law Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLCU Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLCU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLCU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Command Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Status Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Test/ Normal Mode Register . . . . . . . . . . . . . . . . . . . . . . . GHDLC Channel Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC FSC Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . GHDLC Receive Channel Status Registers 0..3 . . . . . . . . . . . . . . . GHDLC Receive Data and Status . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLC Channel Transmit Command Registers . . . . . . . . . . . . . . . ASYNC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCLK0 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCLK1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCLK2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCLK3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Muxes Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHDLCU Frame Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Statistics Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Statistics Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P Interface Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P Mailbox Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . P Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P Mailbox Busy Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P Mailbox Generic Data Register . . . . . . . . . . . . . . . . . . . . . . . . . P Mailbox (General and DMA Mailbox) Data Registers . . . . . . . . . 2003-07-31 PEB 20570 PEB 20571 Table of Contents 6.2.9.5 6.2.9.6 6.2.9.7 6.2.9.8 6.2.10 6.2.10.1 6.2.10.2 6.2.10.3 6.2.11 6.2.11.1 6.2.11.2 6.2.11.3 6.2.11.4 6.2.11.5 6.2.11.6 6.2.11.7 6.2.11.8 6.2.11.9 6.2.11.10 6.2.11.11 6.2.11.12 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.1.1 8.6.1.2 8.6.2 8.6.2.1 8.6.2.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.6.8 Data Sheet Page 225 226 227 228 229 229 230 231 232 232 233 234 235 236 237 238 239 240 241 242 243 DSP Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Mailbox Busy Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Mailbox Generic Data Register . . . . . . . . . . . . . . . . . . . . . . . . DSP Mailbox (General and DMA Mailbox) Data Registers . . . . . . . DMA Mailbox Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Mailbox Transmit Counter Register . . . . . . . . . . . . . . . . . . . . DMA Mailbox Receive Counter Register . . . . . . . . . . . . . . . . . . . . . DMA Mailbox Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . Clock Generator Register Description . . . . . . . . . . . . . . . . . . . . . . . . . PDC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PFS Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCXO Reference Clock Select Register . . . . . . . . . . . . . . . . . . . . . REFCLK Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCL_2000 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L1_CLK Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PFS Sync Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-time Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Strap Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Electrical Characteristics and Timing Diagrams . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended 16.384 MHz Crystal Parameters . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Access Timing In Motorola Mode . . . . . . . . . . . . . . . . . . . . . . DMA Access Timing In Intel/Infineon Mode . . . . . . . . . . . . . . . . . . . mP Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mP Access Timing in Motorola mode . . . . . . . . . . . . . . . . . . . . . . . mP Access Timing in Intel/Infineon Mode . . . . . . . . . . . . . . . . . . . . Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LNC0..3 (Local Network Controller) Interface Timing . . . . . . . . . . . . . JTAG and Emulation Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 245 245 246 247 248 248 249 249 249 252 255 255 257 260 262 266 270 273 277 2003-07-31 PEB 20570 PEB 20571 Table of Contents 9 9.1 9.2 9.3 9.4 10 11 Page 282 282 284 286 287 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELIC Connection to External Microprocessors . . . . . . . . . . . . . . . . . . . DELIC Worksheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Output Driver Anomaly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Data Sheet 2003-07-31 PEB 20570 PEB 20571 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Data Sheet Page Block Diagram of the DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram of the DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DELIC-LC in S/T and UPN Line Cards (up to 8 S/T and 16 UPN). . . . . 7 DELIC-LC/PB in Uk0 Line Card for 16 Subscribers. . . . . . . . . . . . . . . . 8 DELIC-PB in Analog Line Card for 16 Subscribers . . . . . . . . . . . . . . . . 8 DELIC-PB in Small PBX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DELIC-PB in 4 Port SDSL Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Overview of IOM-2000 Interface Structure (Example with One VIP) . . 41 IOM-2000 Data Sequence (1 VIP with 8 Channels) . . . . . . . . . . . . . . 43 IOM-2000 Data Order (3 VIPs with 24 Channels) . . . . . . . . . . . . . . . . 44 IOM-2000 CMD/STAT Handling (1 VIP with 8 Channels) . . . . . . . . . . 45 IOM-2000 Command/Status Sequence (3 VIPs with 24 Channels) . . 45 UPN State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 State Diagram of LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 LT-T Mode State Diagram (Conditional and Unconditional States) . . . 60 IOM(R)-2 Interface in Digital Line Card Mode . . . . . . . . . . . . . . . . . . . . 63 DELIC in Multiplexed and in De-Multiplexed Bus Mode . . . . . . . . . . . 65 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 UPN Interface Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 AMI Coding on the Up Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Handling of UPN Frame (one Channel) . . . . . . . . . . . . . . . . . . . . . . . . 79 S/T Interface Line Code (without code violation) . . . . . . . . . . . . . . . . . 83 Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 84 Reference Clock Selection for Cascaded VIPs on IOM-2000 . . . . . . . 85 Handling of So Frame in LT-S Mode (One Channel) . . . . . . . . . . . . . . 86 D-Echo Bit Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Handling of So Frame in LT-T Mode (One Channel) . . . . . . . . . . . . . . 88 Collision Detection in the LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 90 S/Q Channel Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 IOMU Integration in DELIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 IOMU Frame-Wise Circular-Buffer Architecture. . . . . . . . . . . . . . . . . . 98 The Circular-Buffer During two Consecutive Frames. . . . . . . . . . . . . . 99 IOM-2 Interface Timing in Single/Double Clock Mode . . . . . . . . . . . . 101 IOM-2 Interface Open-Drain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 102 IOM-2 Interface Push-Pull Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DRDY Signal Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DRDY Sampling Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 PCMU Integration in DELIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 IOM-2 Interface Timing in Single/Double Clock Mode . . . . . . . . . . . . 108 2003-07-31 PEB 20570 PEB 20571 List of Figures Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Data Sheet Page A/-law Unit Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 HDLCU General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 HDLC Data Flow in Receive Direction . . . . . . . . . . . . . . . . . . . . . . . . 117 Data Processing in the GHDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 GHDLC Interface Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Point-to-Multi Point Bus Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 GHDLC Receive and Transmit Buffer Structure . . . . . . . . . . . . . . . . 124 Interframe Time Fill with shared Zero . . . . . . . . . . . . . . . . . . . . . . . . 125 Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Two-cycle DMA Transfer Mode for Receive Direction . . . . . . . . . . . . 134 Single cycle DMA transfer mode for Receive Data . . . . . . . . . . . . . . 135 Single cycle DMA transfer mode for Transmit Data . . . . . . . . . . . . . . 136 Timing in two-cycle DMA Mode for Transmit Direction and Infineon/ Intel Bus Type 138 Timing in two-cycle DMA Mode for Receive Direction and Infineon/ Intel Bus Type 140 DELIC Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 TRANSIU Buffer Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 DMA Write-Transaction Timing in Motorola Mode . . . . . . . . . . . . . . . 251 DMA Read-Transaction Timing in Motorola Mode . . . . . . . . . . . . . . . 252 DMA Write-Transaction Timing in Intel/Infineon Mode. . . . . . . . . . . . 254 DMA Read-Transaction Timing in Intel/Infineon Mode . . . . . . . . . . . 254 Write Cycle Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Read Cycle Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Write Cycle Intel/Infineon Demultiplexed Mode . . . . . . . . . . . . . . . . . 258 Read Cycle Intel/Infineon Demultiplexed Mode . . . . . . . . . . . . . . . . . 258 Write Cycle Intel/Infineon Multiplexed Mode . . . . . . . . . . . . . . . . . . . 259 Read Cycle in Intel/Infineon Multiplexed Mode . . . . . . . . . . . . . . . . . 260 Interrupt Acknowledge Cycle Timing in Motorola Mode. . . . . . . . . . . 261 Interrupt Acknowledge Cycle Timing in Intel/Infineon Mode . . . . . . . 261 IREQ Deactivation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 DRDY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 DCL Timing IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 FSC Timing IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 PFS Timing in Slave Mode (Input PCM Clocks) . . . . . . . . . . . . . . . . 267 PFS Timing in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 PFS Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 PDC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 PDC Timing in Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 IOM-2000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 FSC Timing IOM-2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 2003-07-31 PEB 20570 PEB 20571 Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 LNC0..3 (Local Network Controller) Interface Timing . . . . . . . . . . . . LCLK0..3 Timing in Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . LCLK0..3 Timing in Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test-Interface (Boundary Scan) Timing . . . . . . . . . . . . . . . . . . . . . . . Reset Indication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLOCKOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L1_CLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REFCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELIC Connection to Intel 80386EX (Demuxed Configuration) . . . . DELIC Connection to Infineon C165 (Demuxed Configuration). . . . . DELIC-LC PCM Unit Mode 0 (4 Ports with 2 MBit/s) . . . . . . . . . . . . . Command/ Indication Handshake of General Mailbox. . . . . . . . . . . . Behavior of Output Driver if Last Bit is '1' . . . . . . . . . . . . . . . . . . . . . Behavior of Output Driver if Last Bit is '0' . . . . . . . . . . . . . . . . . . . . . Guaranteed Reset Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 275 276 278 279 279 280 280 281 282 283 284 285 286 286 287 Data Sheet 14 2003-07-31 PEB 20570 PEB 20571 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Data Sheet Page IOM(R)-2 Interface Pins (DELIC-LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IOM-2000 Interface / LNC Port 1 (DELIC-LC) . . . . . . . . . . . . . . . . . . . 14 LNC Port 0 (DELIC-LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Microprocessor Bus Interface Pins (DELIC-LC). . . . . . . . . . . . . . . . . . 16 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC) . . . . . . . . . 18 Clock Generator Pins (DELIC-LC) (additionally to IOM/PCM clocks) . 20 Power Supply Pins (DELIC-LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 JTAG and Emulation Interface Pins (DELIC-LC) . . . . . . . . . . . . . . . . . 22 Test Interface Pins (DELIC-LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 IOM(R)-2 Interface Pins (DELIC-PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 IOM-2000 Interface / LNC Port 1 (DELIC-PB) . . . . . . . . . . . . . . . . . . . 26 LNC Port 0 (DELIC-PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Microprocessor Bus Interface Pins (DELIC-PB) . . . . . . . . . . . . . . . . . 28 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) . . . . . . . . . 31 Clock Generator Pins (DELIC-PB) (Additionally to IOM/PCM Clocks). 34 Power Supply Pins (DELIC-PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 JTAG and Emulation Interface Pins (DELIC-PB) . . . . . . . . . . . . . . . . . 36 Test Interface Pins (DELIC-PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Strap Pins (Evaluated During Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Control Bits in S/T Mode on DR Line . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Control Bits in S/T Mode on DX Line . . . . . . . . . . . . . . . . . . . . . . . . . . 42 INFO Structure on UPN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 UPN State Machine Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LT-S State Machine Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LT-T Mode State Machine Codes (Conditional States) . . . . . . . . . . . . 58 TAP Controller Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Differences Between DELIC-LC and DELIC-PB . . . . . . . . . . . . . . . . . 69 D-Echo Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 S/T Mode Multiframe Bit Positions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I-Buffer Logical Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 D-Buffer Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 DCL Frequency in Different IOM-2 Modes. . . . . . . . . . . . . . . . . . . . . 100 I-Buffer Logical Memory Mapping of Input Buffers. . . . . . . . . . . . . . . 106 I-Buffer Logical Memory Mapping of Output Buffers . . . . . . . . . . . . . 106 DSP Access to D-Buffer Input Blocks . . . . . . . . . . . . . . . . . . . . . . . . 106 DSP Access to D-Buffer Output Blocks . . . . . . . . . . . . . . . . . . . . . . . 107 PCM TSC in 4 x 32 TS Mode (4 x 2 MBit/s) . . . . . . . . . . . . . . . . . . . 109 PCM TSC in 2 x 64 TS Mode (2 x 4MBit/s) . . . . . . . . . . . . . . . . . . . . 109 PCM TSC in 1 x 128 TS (1 x 8 MBit/s) and 1 x 256 TS (1 x 16 MBit/s) (1st Half) Mode 110 PCM TSC in 1 x 256 TS (1 x 16 MBit/s) (2nd Half) Mode . . . . . . . . . 110 GHDLCU Receive Buffer Configuration . . . . . . . . . . . . . . . . . . . . . . . 123 2003-07-31 PEB 20570 PEB 20571 List of Tables Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Data Sheet Page Interrupt Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Overview of Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 DSP Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 DSP Program Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Occupied DSP Data Address Space . . . . . . . . . . . . . . . . . . . . . . . . . 147 OAK Memory Mapped Registers Address Space . . . . . . . . . . . . . . . 148 P Address Space Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 TRANSIU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Scrambler Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 IOMU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 PCMU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 A-/-Law Unit Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 HDLCU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 GHDLC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 DCU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 P Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 General Mailbox Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 DMA Mailbox Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Clock Generator Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Available ISDN Modes for Each VIP Channel . . . . . . . . . . . . . . . . . . 162 Tristate Control Assignment for IOM-2 Time Slots. . . . . . . . . . . . . . . 180 R/W Behavior During DMA Transactions in Normal and in Fly-By Mode . 249 DMA Transaction timing in Motorola Mode . . . . . . . . . . . . . . . . . . . . 250 R/W Behavior During DMA Transactions in Normal and in Fly-By Modes. 253 DMA Transaction Timing in Intel/Infineon Mode . . . . . . . . . . . . . . . . 253 Timing for Write Cycle in Motorola Mode . . . . . . . . . . . . . . . . . . . . . . 255 Timing for Read Cycle In Motorola Mode . . . . . . . . . . . . . . . . . . . . . 256 Timing for Write Cycle in Intel/Infineon Demultiplexed Mode. . . . . . . 257 Timing For Read Cycle in Intel/Infineon Demultiplexed Mode . . . . . . 258 Timing for Write Cycle in Intel/Infineon Multiplexed Mode . . . . . . . . . 259 Timing For Read Cycle in Intel/Infineon Multiplexed Mode . . . . . . . . 260 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . 261 IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 DCL (IOM-2 Data Clock) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 FSC (IOM-2 and IOM-2000 Frame-Sync) Timing . . . . . . . . . . . . . . . 264 PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 PDC (PCM Data Clock) Timing in Master Mode (Output Mode) . . . . 268 PDC Timing in Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 IOM-2000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 DCL_2000 (IOM-2000 Data Clock) Timing . . . . . . . . . . . . . . . . . . . . 272 2003-07-31 PEB 20570 PEB 20571 List of Tables Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Page 273 275 275 276 277 278 279 279 280 281 LNC0..3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCLK0..3 Timing in Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . LCLK0..3 Timing in Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DSP Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset and RESIND (Reset Indication) timing . . . . . . . . . . . . . . . . . . CLOCKOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L1_CLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REFCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 2003-07-31 PEB 20570 PEB 20571 Preface This document provides reference information on the DELIC-LC/-PB Version 3.1. Organization of this Document This Data Sheet is divided into 11 chapters and appendices. It is organized as follows: * Chapter 1 Introduction Gives a general description of the product and its family, lists the key features, and presents some typical applications. * Chapter 2 Pin Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. * Chapter 3 Interface Description Describes the DELIC external interfaces. * Chapter 4 Functional Description Describes the features of the main functional blocks. * Chapter 5 DELIC Memory Structure Containes the memory organisation of the OakDSPCore(R). * Chapter 6 Register Description Containes the detailed register description. * Chapter 7 Package Outlines * Chapter 8 Electrical Characteristics and Timing Diagrams Containes the DC specification. Contains the AC specification. * Chapter 9 Application Hints Provides e.g. a worksheet * Chapter 10 Glossary * Chapter 11 Index Your Comments We welcome your comments on this document as we are continuously aiming at improving our documentation. Please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (DELIC-LC/ -PB), device number (PEB 20570/PEB 20571), device version (Version 3.1), or and in the body of your e-mail: document type (Data Sheet), issue date (2003-07-31) and document revision number (DS 2.1). Data Sheet 1 2003-07-31 PEB 20570 PEB 20571 Introduction 1 Introduction The DELIC and VIP chipset realizes multiple ISDN S/T and UPN interfaces together with controller functionality typically needed in PBX or Central Office systems. This functionality comprises voice channel handling, signaling control, layer-1 control, and even signal processing tasks. Moreover it provides a programmable master/slave clock generator with 2 PLLs, an universal P interface and a DMA interface. The controller part, DELIC, is available in two different versions: * DELIC-LC (PEB 20570) is a line card controller providing voice channel switching, multiple HDLC and layer-1 control for up to three VIPs (24 ISDN channels). Other transceiver ICs (32 analog or 16 digital channels) may additionally be connected via IOM-2/GCI interface. * DELIC-PB (PEB 20571) additionally provides a programmable telecom DSP including program and data RAM. This DSP can be used for layer-1 control, protocol support and signal processing. The flexibility gained by the programmability allows Infineon to offer different application specific solutions with the same silicon just by software configuration. A configuration tool assists the user in finding a valid system configuration. Even more customer specific DSP-routines can be integrated with the assistance of Infineon. The transceiver part, VIP, is available in two different versions: * VIP PEB 20590 is the first (8 channel) ISDN transceiver that implements multiple UPN and S/T interfaces within one device. The user can decide by programming in which mode a desired channel shall work. A total of 8 channels are provided for layer-1 subscriber or trunk line characteristic. The VIP is programmed by the DELIC via the IOM-2000 interface. VIP's eight channels are programmable in the following maximum partitioning between UPN and S/T channels: Max. number of UPN and S/T Channels UPN S/T 8 0 7 1 6 2 5 3 4 4 * VIP-8 PEB 20591 Additionally to the features of the VIP, the VIP-8 allows any combination of UPN S/T interface (i.e. each of the 8 channels may be programmed to S/T or UPN mode) Data Sheet 2 2003-07-31 PEB 20570 PEB 20571 Introduction Block diagrams: DELIC-LC IOM-2 / PCM Interface IOM-2 / PCM IOM - 2000 IOM-2000 Interface 24 HDLC Controllers Signaling Controller Clocks P Mailbox JTAG P Interface DELIC-LC-PB1.vsd Figure 1 Block Diagram of the DELIC-LC DELIC-PB IOM-2 / PCM Interface IOM-2 / PCM Program RAM IOM - 2000 DSP Voice handling Data RAM IOM-2000 Interface 32 HDLC Controllers Async/Sync Controller Clocks P Mailbox DMA Mailbox JTAG P Interface DSP Emulation Interface Figure 2 Block Diagram of the DELIC-PB Data Sheet 3 Serial Port/ I/O-ports DELIC-LC-PB.vsd PCM Switch PCM Interface Serial Port/ I/O-ports PCM Switch 256 x 256 TS PCM Interface 2003-07-31 DSP Embedded Line and Port Interface Controller DELIC-LC DELIC-PB PEB 20570 PEB 20571 Version 3.1 CMOS 1.1 DELIC-LC Key Features DELIC-LC is optimized for line card applications: * One IOM-2000 interface supporting three VIPs i.e. up to 24 ISDN channels * Two IOM-2 (GCI) ports (configurable as PCM ports) supporting up to 16 ISDN channels or 32 analog subscribers * Four PCM ports with up to 4 x 2.048 Mbit/s P-TQFP-100-3 (4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s * Switching matrix 256 x 256 TS (8-bit switching) * 24 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s) * Serial communication controller: high-speed signaling channel for 2.048 Mbit/s * General purpose I/O ports * Standard multiplexed and de-multiplexed P interface: Infineon, Intel, Motorola * Programmable PLL based Master/Slave clock generator, providing all system clocks from a single 16.384 MHz crystal source * JTAG compliant test interface * single 3.3 V power supply, 5 V tolerant inputs 1.2 DELIC-PB Key Features Compared to the DELIC-LC, having a fixed functionality, the DELIC-PB provides a high degree of flexibility (in terms of selected number of ports or channels). Additionally it features computing power for typical DSP-oriented PBX tasks like conferencing, DTMF etc. A Microsoft Windows based configuration tool, the Configurator, enables to generate an application specific functionality. Its features are mainly determined by the firmware of the integrated telecom DSP. Type PEB 20571/ PEB 20570 Data Sheet 4 Package P-TQFP-100-3 2003-07-31 PEB 20570 PEB 20571 Introduction List of maximum available features: * One IOM-2000 interface supporting up to three VIPs i.e. up to 24 ISDN channels * Support of DASL mode * Up to two IOM-2 (GCI) ports (also configurable as PCM ports) supporting up to 16 ISDN channels or 32 analog subscribers * Up to four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s * Switching matrix 256 x 256 TS (switching of 4-/8- bit time slots) * Up to 32 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s) * Up to 4 serial communication controllers: one of them with up to 8.192 Mbit/s data rate * General purpose I/O ports * DECT synchronization support * Standard multiplexed and de-multiplexed P interface: Infineon, Intel, Motorola * Dedicated DMA support mailbox for 2 DMA-channels * Integrated DSP core OAK+ (60 MIPS for layer 1 control, signalling and DSPalgorithms) * 4 kWord on-chip program memory * 2 kWord on-chip data memory * 2 kWord ROM * DSP work load measurement for run-time statistics, DSP alive indication * On chip debugging unit * Serial DSP program debugging interface connected via JTAG port * A-/-law conversion unit * Programmable PLL based Master/Slave clock generator, providing all system clocks from a single 16.384 MHz crystal source * JTAG compliant test interface * single 3.3 V power supply, 5 V compatible inputs Note: As each feature consumes system resources (DSP-MIPS, memory, port pins), the maximum available number of supported interfaces or HDLC channels is limited by the totally available resources. A System Configurator tool (see DELIC Software User's Manual) helps to determine a valid configuration. Data Sheet 5 2003-07-31 PEB 20570 PEB 20571 Introduction 1.3 Logic Symbol P-TQFP-100-3 Power Supply 27 IOM-2 Interfaces 7 14 IOM-2000/ LNC Interface 5 DELIC-LC PEB20570 DELIC-PB PEB 20571 5 PCM/ LNC Interfaces Clock Signals 9 LNC or Signaling Interface P-TQFP-100-3 26 5 2 P Interface JTAG Interface Test Interface DELIC-logic-DS.vsd Figure 3 Logic Symbol Data Sheet 6 2003-07-31 PEB 20570 PEB 20571 Introduction 1.4 1.4.1 Typical Applications Applications for DELIC-LC The following two figures show example configurations of DELIC-LC Line card applications for different ISDN interface standards. In Figure 4, three VIP transceiver ICs are connected to the DELIC-LC via the IOM-2000 interface, whereas in Figure 5 and Figure 6 an IOM-2 (GCI) interface is used to connect other ISDN transceivers. up to 4x S/T 4x Upn VIP PEB 20590 IOM-2000 PCM 4 x 32 TS DELIC-LC up to 4x S/T 4x Upn PEB 20570 VIP PEB 20590 Signaling up to 2.048 Mbit/s 8x Upn VIP PEB 20590 P Infineon C166 Memory Figure 4 DELIC-LC in S/T and UPN Line Cards (up to 8 S/T and 16 UPN) Data Sheet 7 2003-07-31 PEB 20570 PEB 20571 Introduction HYBRID HYBRID AFE/ DFE IOM-2 . . . DELIC-LC/PB PEB 20570 (PEB 20571) PCM 4 x 32 TS HYBRID HYBRID AFE/ DFE 16 x Uk0 HYBRID AFE/ DFE HYBRID HYBRID . . . Signaling AFE/ DFE HYBRID Memory P Infineon C166 Figure 5 DELIC-LC/PB in Uk0 Line Card for 16 Subscribers Note: In this application DELIC-PB is also meaningful. 1.4.2 Applications for DELIC-PB HV-SLIC HV-SLIC SLICOFI-2 IOM-2 PCM 4 x 32 TS SLICOFI-2 DELIC-PB IOM-2 HV-SLIC HV-SLIC 16 x t/r HV-SLIC PEB 20571 SLICOFI-2 HV-SLIC HV-SLIC SLICOFI-2 HV-SLIC Signaling Memory P Infineon C166 Figure 6 DELIC-PB in Analog Line Card for 16 Subscribers Data Sheet 8 2003-07-31 PEB 20570 PEB 20571 Introduction HV-SLIC HV-SLIC SLICOFI-2 IOM-2 PCM up to 32 TS 32 x t/r HV-SLIC HV-SLIC SLICOFI-2 DELIC-PB PEB 20571 VIP PEB 20590 IOM-2000 4x UPN 2xS Central Office 2xT LNC 2 Mbit/s for service Power Supply Memory P Infineon C166 Figure 7 DELIC-PB in Small PBX 2.3 MBit/s 0 SOCRATES 0 DELIC-PB PEB 20571 8.192 Mbit/s PCM IOM-2 4.096 Mbit/s 1 SOCRATES 1 ASIC Voice REFCLK 8.192 Mbit/s PCM PCM 8.192 Mbit/s Data 2 SOCRATES 2 3 SOCRATES 3 C165 Memory Figure 8 DELIC-PB in 4 Port SDSL Line Card Data Sheet 9 2003-07-31 PEB 20570 PEB 20571 Pin Description 2 2.1 Pin Description Pin Diagram DELIC-LC (top view) P-TQFP-100-3 DCL_2000/ LRTS1 LTSC0/ LRTS0 LCxD0/LCTS0 TRST TMS TDI/ SCANEN STAT/ LCTS1 RxD2/ LCTS2 RxD3/ LCTS3 CMD/ LCLK1 RxD1/LRxD3 DSP_STOP DX/ LTxD1 DR/ LRxD1 LRxD0 LCLK0 LTxD0 JTCK VDD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RxD0/LRxD2 TSC0/ LRTS2 TXD0/LTxD2 TSC1/ LRTS3 TxD1/LTxD3 TSC2 TxD2/LCLK2 TSC3 VDD VSS TxD3/LCLK3 PFS PDC RESIND REFCLK VDD VSS VSSA CLK16-XI CLK16-XO VDDA VSSA VSSA VDDA VDDA 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TDO VSS VDD VDD VSS VSS DELIC-LC PEB 20570 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1718 19 20 2122 23 2425 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 SCANMO VSS L1_CLK VSS VDD DRDY DD1 DD0 DU1 DU0 DCL FSC A6 VSS VDD A5 A4 A3 A2 A1 A0 RESET CLKOUT VSS VDD CLK_DSP DSP_FRQ WR / R/W DCXOPD DREQT RD / DS IREQ MODE DREQR XCLK IACK VDD ALE VSS VDD VSS D3 CS D0 D1 D2 D4 Figure 9 Data Sheet Pin Configuration DELIC-LC 10 2003-07-31 D5 D6 D7 PEB 20570 PEB 20571 Pin Description 2.2 Pin Diagram DELIC-PB (top view) P-TQFP-100-3 DCL_2000/ LTSC1/LRTS1 STAT/ LCxD1/LCTS1 RxD2/ LCxD2/LCTS2 RxD3/ LCxD3/LCTS3 LTSC0/ LRTS0 LCxD0/LCTS0 TRST TMS TDI/ SCANEN DR/ LRxD1 CMD/ LCLK1 RxD1/LRxD3 DSP_STOP DX/ LTxD1 LRxD0 LCLK0 LTxD0 JTCK VDD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RxD0/LRxD2 TSC0/ LTSC2/LRTS2 TXD0/LTxD2 TSC1/ LTSC3/LRTS3 TxD1/LTxD3 TSC2 TxD2/LCLK2 TSC3 VDD VSS TxD3/LCLK3 PFS PDC RESIND REFCLK VDD VSS VSSA CLK16-XI CLK16-XO VDDA VSSA VSSA VDDA VDDA 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TDO VSS VDD VDD VSS VSS DELIC-PB PEB 20571 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 2122 23 2425 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 SCANMO VDD L1_CLK VSS VDD DRDY DD1 DD0 DU1 DU0 DCL FSC A6 VSS VDD A5 A4/DACK A3 A2 A1 A0 RESET CLKOUT VSS VDD CLK_DSP DSP_FRQ WR / R/W DCXOPD DREQT RD / DS MODE XCLK IREQ DREQR IACK VDD ALE VDD VSS VSS D3 CS D0 D2 D4 Figure 10 Pin Configuration DELIC-PB Data Sheet 11 D5 D6 D7 D1 2003-07-31 PEB 20570 PEB 20571 Pin Description 2.3 Pin Definitions and Functions for DELIC-LC Note: The column "During Reset" refers to the time period that starts with activation of RESET input and ends with the deactivation of the RESIND output. During this period, the DELIC strap pins (refer to Table 19) may be driven by external pulldown or pull-up resistors to define DELIC configuration. If external pull-down or pull-up resistors are not connected to the strap pins, the value of each strap pin during reset will be determined by an internal pull-up or pull-down resistor, according to the default strap value of each pin. The user must ensure that connected circuits do not influence the sampling of the strap pins during reset. The column "After Reset" describes the behavior of every pin, from the deactivation of the RESIND output until the DELIC registers are programmed. Note: In order to garantee the reset behaviour of every pin please refer to the application hint "Reset Behaviour" on Page 287. Data Sheet 12 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 1 Pin No. 39 IOM(R)-2 Interface Pins (DELIC-LC) In (I) During Out(O) Reset O O After Reset O Function Frame Synchronization Clock (8 kHz) Used for both the IOM-2 and the IOM2000 interface IOM-2 Data Clock 2.048 MHz or 4.096 MHz Symbol FSC 40 DCL O TESTStrap (3), (pull-up), refer to Table 19 High Z High Z I I I O 43 44 41 42 45 DD0 DD1 DU0 DU1 DRDY O(OD) O(OD) I I I High Z Data Downstream IOM-2 Interface Channel0 High Z Data Downstream IOM-2 Interface Channel1 I I I Data Upstream IOM-2 Interface Channel 0 Data Upstream IOM-2 Interface Channel 1 D- Channel Ready Stop/Go information for D-channel control on S/T interface in LT-T. Affects only IOM-2 port 0. DRDY = 1 means GO DRDY = 0 means STOP If DRDY is not used, this pin has to be connected to 'High' level Data Sheet 13 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 2 Pin No. 70 IOM-2000 Interface / LNC Port 1 (DELIC-LC) In (I) During After Out (O) Reset Reset O O Function IOM-2000 Data Clock 3.072, 6.144 or 12.288 MHz 'request-to-send' functionality (Async mode) High Z High Z Data Transmit Transmits IOM-2000 data to VIP LNC Transmit Serial Data Port 1 (Async mode). I I Data Receive Receives IOM-2000 data from VIP LNC Receive Serial Data Port 1 (Async mode). High Z High Z IOM-2000 Command Transmits DELIC commands to VIP. LNC Clock Port 1. When configured as output may be driven at the following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz I I IOM-2000 Status Receives status information from VIP. LNC1 Clear to Send 'clear-to-send' functionality (Async mode) Symbol DCL_2000 / O LRTS1 69 DX / O O LTxD1 68 DR / O (OD) I LRxD1 67 CMD / I O LCLK1 I/O 64 STAT / I LCTS1 I Data Sheet 14 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 3 Pin No. 62 61 60 LNC Port 0 (DELIC-LC) After Reset I Function LNC Receive Serial Data Port 0 (HDLC and Async mode). Symbol In (I) During Out (O) Reset LRxD0 LTxD0 I O (OD) I High Z High Z LNC Transmit Serial Data Port 0 (HDLC and Async mode). LNC0 Tristate Control / Request to Send 2 modes per S/W selectable: 1) TxD output is valid (HDLC mode). Supplies a control signal for an external driver. ('low' when the corresponding TxD-output is valid). 2) 'request-to-send' functionality (Async mode) LNC0 Collision Data / Clear to Send 2 modes per S/W selectable: 1) Collision Data (HDLC Mode). 2) 'clear-to-send' functionality (Async mode) LTSC0 / O LRTS0 H PLLBypass" strap. Pull-up refer to Page 38 59 LCxD0 / I LCTS0 I I 56 LCLK0 I/O I I LNC Clock Port 0 When configured as output may be driven at the following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz . Data Sheet 15 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 4 Pin No. 25 24 23 22 21 18 17 16 38 35 34 33 32 31 30 11 Microprocessor Bus Interface Pins (DELIC-LC) After Reset Function Data Bus When operated in address/data multiplex mode, this bus is used as a multiplexed AD bus. The Address pins are externally connected to the AD bus. Symbol In (I) During Out (O) Reset D7 D6 D5 D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 A1 A0 I/O The direction of these pins depends on the value of the following pins: CS, RD/DS, WR / R/W and MODE I I I Address Bus (bits 6 ... 0) When operated in address/data multiplex mode, this bus is used as a multiplexed AD bus. The Data pins are externally connected to the AD bus. DREQR O L CLOCK MASTER Strap (pulldown), refer to Table 19 L EMULATION BOOT Strap (pulldown), refer to Table 19 I I Strap pin 10 DREQT O Strap pin 12 CS I Chip Select A "low" on this line selects all registers for read/write operations. Write (Intel/Infineon Mode) Indicates a write access. Read/Write (Motorola Mode) Indicates the direction of the data transfer 13 WR/ I I I R/W Data Sheet 16 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 4 Pin No. 14 Microprocessor Bus Interface Pins (DELIC-LC) (cont'd) After Reset I Function Read (Intel/Infineon Mode) Indicates a read access. Data Strobe (Motorola Mode) During a read cycle, DS indicates that the DELIC should place valid data on the bus. During a write access, DS indicates that valid data is on the bus. I I I Address Latch Enable Controls the on-chip address latch in multiplexed bus mode. While ALE is 'high', the latch is transparent. The falling edge latches the current address. ALE is also evaluated to determine the bus mode ('low'=multiplexed, 'high'=demultiplexed) Bus Mode Selection Selects the P bus mode ('low'=Intel/Infineon, 'high'=Motorola) Symbol In (I) During Out (O) Reset RD/ I I DS 15 ALE 7 MODE I I I 6 IREQ O (OD) High Z (OD) High Z Interrupt Request is programmable to (OD) push/pull (active high or low) or opendrain. This signal is activated when the DELIC requests a P interrupt. When operated in open drain mode, multiple interrupt sources may be connected. I I O Interrupt Acknowledge System Reset DELIC is forced to go into reset state. Reset Indication Indicates that the DELIC is executing a reset. The DELIC remains in reset state for at least 500 s after the termination of the RESET pulse. 5 29 89 IACK RESET I I I I O RESIND O Data Sheet 17 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 5 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC) After Reset I Function PCM Frame Synchronization Clock. 8 kHz/4 kHz when input or 8 kHz when output. Note: When PFS is configured as 4 kHz input, PDC configuration is restricted to 2.048 MHz input. 88 PDC I/O I I PCM Data Clock (input or output) 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz PCM Receive Data Port 0 LNC Receive Serial Data Port 2 (Async mode) High Z High Z PCM Transmit Data Port 0 LNC Transmit Serial Data Port 2 Async mode) H Reset Counter Bypass" strap pull-up refer to Page 38 PCM Tristate Control Port 0 Supplies a control signal for an external driver ('low' when the corresponding TxDoutput is valid). LNC2 Request To Send 'request-to-send' functionality (Async mode) 74 RxD2 / LCTS2 82 TxD2 / LCLK2 I I O I/O weak low weak low I I PCM Receive Data Port 2 LNC2 'clear-to-send' functionality (Async mode) PCM Transmit Data Port 2 LNC External Clock Port 2 When configured as output may be driven at the following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz 18 2003-07-31 Pin Symbol In (I) During No. Out (O) Reset 87 PFS I/O I 76 RxD0 / LRxD2 I I O O(OD) O I I 78 TxD0 / LTxD2 77 TSC0 / LRTS2 O Data Sheet PEB 20570 PEB 20571 Pin Description Table 5 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC) (cont'd) After Reset Function PCM Tristate Control Port 2 Supplies a control signal for an external driver ('low' when the corresponding TxDoutput is valid). PCM Receive Data Port 1 LNC Receive Serial Data Port 3 (Async mode) High Z High Z PCM Transmit Data Port 1 LNC Transmit Serial Data Port 3 (Async mode) PLL H PowerDown strap pull-up refer to Page 38 I I PCM Tristate Control Port 1 Supplies a control signal for an external driver ('low' when the corresponding TxDoutput is valid). LNC3 Request to Send 'request-to-send' functionality (Async mode) PCM Receive Data Port 3 LNC3 'clear-to-send' functionality (Async mode) weak low weak low PCM Transmit Data Port 3 LNC External Clock Port 3 When configured as output may be driven at the following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz TEST(1) H strap refer to Page 38 PCM Tristate Control Port 3 Supplies a control signal for an external driver ('low' when the corresponding TxD output is valid). Pin Symbol In (I) During No. Out (O) Reset 81 TSC2 O TEST(1) H strap refer to Page 38 I I 75 RxD1 / LRxD3 I I O O(OD) O 80 TxD1 / LTxD3 79 TSC1 / LRTS3 71 RxD3 / LCTS3 I I O I/O 86 TxD3 / LCLK3 83 TSC3 O Data Sheet 19 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 6 Pin No. 94 95 1 Clock Generator Pins (DELIC-LC) (additionally to IOM/PCM clocks) In (I) During After Function Out (O) Reset Reset I O I I O I I O I 16.384 MHz External Crystal Input 16.384 MHz External Crystal Output DCXO Power Down and Bypass Activating this input powers down the on-chip DCXO PLL. The input CLK16-XI is used directly as the internal 16.384 MHz clock, and the oscillator and the shaper are bypassed. Required for testing; during normal operation this input should be permanently low (`0'). External DSP Clock Provides a DSP clock other than 61.44 MHz from an external oscillator. DSP Operational Frequency Selection (e.g. for test purpose) 0: The DSP is clocked internally at 61.44 MHz 1: The DSP clock is driven by the CLK_DSP input pin Layer-1 Clock 15.36 MHz or 7.68 MHz General Purpose Clock Output 2.048 MHz, 4.096 MHz, 8.192 MHz, 15.36 MHz or 16.384 MHz External Reference Clock Synchronization input from Layer-1 ICs (8 kHz, 512 kHz or 1.536 MHz) This pin is connected to the VIP's REFCLK output at 1.536 MHz. Reference Clock Input: Synchronization of DELIC clock system Output: Used to drive a fraction of XCLK to the system clock master (8 kHz or 512 kHz programmable) Symbol CLK16-XI CLK16-XO DCXOPD 2 CLK_DSP I I I 3 DSP_FRQ I I I 48 28 L1_CLK CLKOUT O O O O O O 4 XCLK I I I 90 REFCLK I/O I I Data Sheet 20 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 7 Pin No. 8 19 26 36 46 57 65 72 84 91 9 20 27 37 47 49 58 66 73 85 92 96 99 100 93 97 98 Power Supply Pins (DELIC-LC) Symbol VDD In (I) During After Out (O) Reset Reset I I I Function Power Supply 3.3 V Used for core logic and interfaces in pure 3.3 V environment VSS I I I Digital Ground (0 V) VDDA I I I Power Supply 3.3 V Analog Logic Used for DCXO and PLL Analog Ground Used for DCXO and PLL VSSA I I I Data Sheet 21 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 8 Pin Symbol No. 54 JTCK JTAG and Emulation Interface Pins (DELIC-LC) In (I) During After Out (O) Reset Reset I I I Function Used for boundary scan according to IEEE 1149.1 JTAG Test Clock Provides the clock for JTAG test logic. Used also for serial emulation interface. Test Mode Select A '0' to '1' transition on this pin is required to step through the TAP controller state machine. Test Data Input In the appropriate TAP controller state test data or a instruction is shifted in via this line. Used also for serial emulation interface. This pin must not be driven to low on the board during reset and operation to ensure functioning of DELIC SCAN Enable When both SCANMO and SCANEN are asserted, the full-scan tests of DELIC are activated. Not used during normal operation. Test Data Output In the appropriate TAP controller state test data or an instruction is shifted out via this line. Used also for serial emulation interface. Test Reset Provides an asynchronous reset to the TAP controller state machine. DSP Stop Pin Stops external logic during breakpoints. Activated when a stop to the DSP is issued. 53 TMS I I I 52 TDI / I I I SCANEN 51 TDO O O O 55 TRST I I I 63 DSP_STOP O BOOT O Strap (pulldown) refer to Table 19 Data Sheet 22 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 9 Pin No. 50 Test Interface Pins (DELIC-LC) In (I) During Out (O) Reset I I After Reset I Function Scan Mode If driven to '1' during device tests, TDI input is used as enable for full scan tests of the DELIC. SCANMO should be tied to GND during normal operation. Symbol SCANMO Data Sheet 23 2003-07-31 PEB 20570 PEB 20571 Pin Description 2.4 Pin Definitions and Functions for DELIC-PB Note: The column "During Reset" refers to the time period that starts with activation of RESET input and ends with the deactivation of the RESIND output. During this period, the DELIC strap pins (refer to Table 19) may be driven by external pulldown or pull-up resistors to define DELIC configuration. If external pull-down or pull-up resistors are not connected to the strap pins, the value of each strap pin during reset will be determined by an internal pull-up or pull-down resistor, according to the default strap value of each pin. The user must ensure that connected circuits do not influence the sampling of the strap pins during reset. The column "After Reset" describes the behavior of every pin, from the deactivation of the RESIND output until the DELIC registers are programmed. Note: In order to garantee the reset behaviour of every pin please refer to the application hint "Reset Behaviour" on Page 287. Data Sheet 24 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 10 Pin No. 39 IOM(R)-2 Interface Pins (DELIC-PB) In (I) During Out(O) Reset O O After Reset O Function Frame Synchronization Clock (8 kHz) Used for both the IOM-2 and the IOM2000 interface IOM-2 Data Clock 2.048 MHz or 4.096 MHz Symbol FSC 40 DCL O TESTStrap (3), (pull-up), refer to Table 19 High Z High Z I I I O 43 44 41 42 45 DD0 DD1 DU0 DU1 DRDY O(OD) O(OD) I I I High Z Data Downstream IOM-2 Interface Channel0 High Z Data Downstream IOM-2 Interface Channel1 I I I Data Upstream IOM-2 Interface Channel 0 Data Upstream IOM-2 Interface Channel 1 D- Channel Ready Stop/Go information for D-channel control on S/T interface in LT-T. Affects only IOM-2 port 0. DRDY = 1 means GO DRDY = 0 means STOP If DRDY is not used, this pin has to be connected to 'High' level Data Sheet 25 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 11 Pin No. 70 IOM-2000 Interface / LNC Port 1 (DELIC-PB) In (I) During After Out (O) Reset Reset O O Function IOM-2000 Data Clock 3.072, 6.144 or 12.288 MHz LNC1 Tristate Control /Request to Send 2 modes per S/W selectable: 1) TxD output is valid (HDLC mode). Supplies a control signal for an external driver. ('low' when the corresponding TxD-output is valid). 2) 'request-to-send' functionality (Async mode) High Z High Z Data Transmit Transmits IOM-2000 data to VIP LNC Transmit Serial Data Port 1 (HDLC and Async mode). I I Data Receive Receives IOM-2000 data from VIP LNC Receive Serial Data Port 1 (HDLC and Async mode). High Z High Z IOM-2000 Command Transmits DELIC commands to VIP. LNC Clock Port 1. When configured as output may be driven at the following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz I I IOM-2000 Status Receives status information from VIP. LNC1 Collision Data / Clear to Send 1) Collision Data (HDLC Mode). 2) 'clear-to-send' functionality (Async mode) Symbol DCL_2000 / O LTSC1/ LRTS1 O 69 DX / O LTxD1 68 DR / O (OD) I LRxD1 67 CMD / I O LCLK1 I/O 64 STAT / I LCxD1/ LCTS1 I Data Sheet 26 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 12 Pin No. 62 61 60 LNC Port 0 (DELIC-PB) After Reset I Function LNC Receive Serial Data Port 0 (HDLC and Async mode). Symbol In (I) During Out (O) Reset LRxD0 LTxD0 I O (OD) I High Z High Z LNC Transmit Serial Data Port 0 (HDLC and Async mode). LNC0 Tristate Control / Request to Send 2 modes per S/W selectable: 1) TxD output is valid (HDLC mode). Supplies a control signal for an external driver. ('low' when the corresponding TxD-output is valid). 2) 'request-to-send' functionality (Async mode) LNC0 Collision Data / Clear to Send 2 modes per S/W selectable: 1) Collision Data (HDLC Mode). 2) 'clear-to-send' functionality (Async mode) LTSC0 / O LRTS0 H PLLBypass" strap. pull-up refer to Page 38 59 LCxD0 / I LCTS0 I I 56 LCLK0 I/O I I LNC Clock Port 0 When configured as output may be driven at the following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz Data Sheet 27 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 13 Pin No. 25 24 23 22 21 18 17 16 38 35 33 32 31 30 34 Symbol D7 D6 D5 D4 D3 D2 D1 D0 A6 A5 A3 A2 A1 A0 A4 DACK/ I I I Microprocessor Bus Interface Pins (DELIC-PB) In (I) During Out (O) Reset After Reset Function Data Bus When operated in address/data multiplex mode, this bus is used as a multiplexed AD bus. The Address pins are externally connected to the AD bus. I/O The direction of these pins depends on the value of the following pins: CS, RD/DS, WR / R/W and MODE I I I Address Bus (bits 6 ... 0 except bit 4) When operated in address/data multiplex mode, this bus is used as a multiplexed AD bus. The Data pins are externally connected to the AD bus. Bit 4 of the address bus/ DMA Acknowledge In non-DMA mode DACK/A4 input pin should be connected to A4 of the P address-bus. In DMA mode A4 is internally connected to `0'. DMA Request for Receive Direction May be configured to active high or active low (the default is active high) 11 DREQR O L CLOCK MASTER Strap (pulldown), refer to Table 19 L EMULATION BOOT Strap (pulldown), refer to Table 19 10 DREQT O DMA Request for Transmit Direction May be configured to active high or active low (the default is active high) Data Sheet 28 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 13 Pin No. 12 Symbol CS Microprocessor Bus Interface Pins (DELIC-PB) (cont'd) In (I) During Out (O) Reset I I After Reset I Function Chip Select A "low" on this line selects all registers for read/write operations. Write (Intel/Infineon Mode) Indicates a write access. Read/Write (Motorola Mode) Indicates the direction of the data transfer I I I Read (Intel/Infineon Mode) Indicates a read access. Data Strobe (Motorola Mode) During a read cycle, DS indicates that the DELIC should place valid data on the bus. During a write access, DS indicates that valid data is on the bus. I I I Address Latch Enable Controls the on-chip address latch in multiplexed bus mode. While ALE is 'high', the latch is transparent. The falling edge latches the current address. ALE is also evaluated to determine the bus mode ('low'=multiplexed, 'high'=demultiplexed) Bus Mode Selection Selects the P bus mode ('low'=Intel/Infineon, 'high'=Motorola) 13 WR/ I I I R/W 14 RD/ DS 15 ALE 7 MODE I I I 6 IREQ O (OD) High Z (OD) High Z Interrupt Request is programmable to (OD) push/pull (active high or low) or opendrain. This signal is activated when the DELIC requests a P interrupt. When operated in open drain mode, multiple interrupt sources may be connected. I Interrupt Acknowledge 5 IACK I I Data Sheet 29 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 13 Pin No. 29 89 Symbol RESET Microprocessor Bus Interface Pins (DELIC-PB) (cont'd) In (I) During Out (O) Reset I I O After Reset I O Function System Reset DELIC is forced to go into reset state. Reset Indication Indicates that the DELIC is executing a reset. The DELIC remains in reset state for at least 500 s after the termination of the RESET pulse. RESIND O Data Sheet 30 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 14 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) After Reset I Function PCM Frame Synchronization Clock. 8 kHz/4 kHz when input or 8 kHz when output. Note: When PFS is configured as 4 kHz input, PDC configuration is restricted to 2.048 MHz input. 88 PDC I/O I I PCM Data Clock (input or output) 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz PCM Receive Data Port 0 LNC Receive Serial Data Port 2 (HDLC and Async mode) High Z High Z PCM Transmit Data Port 0 LNC Transmit Serial Data Port 2 (HDLC and Async mode) H Reset Counter Bypass" strap pull-up refer to Page 38 PCM Tristate Control Port 0 Supplies a control signal for an external driver ('low' when the corresponding TxDoutput is valid). LNC2 Tristate Control / Request To Send 2 modes per S/W selectable: 1) TxD output is valid (HDLC mode). Supplies a control signal for an external driver. ('low' when the corresponding TxDoutput is valid). 2) 'request-to-send' functionality (Async mode) Pin Symbol In (I) During No. Out (O) Reset 87 PFS I/O I 76 RxD0 / LRxD2 I I O O(OD) O I I 78 TxD0 / LTxD2 77 TSC0 / LTSC2/ LRTS2 O Data Sheet 31 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 14 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) (cont'd) After Reset I Function PCM Receive Data Port 2 LNC2 Collision Data 2 modes per S/W selectable: 1) Collision Data (In HDLC Mode). 2) 'clear-to-send' functionality (Async mode) weak low weak low PCM Transmit Data Port 2 LNC External Clock Port 2 When configured as output may be driven at the following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz TEST(1) H strap refer to Page 38 I I PCM Tristate Control Port 2 Supplies a control signal for an external driver ('low' when the corresponding TxDoutput is valid). PCM Receive Data Port 1 LNC Receive Serial Data Port 3 (HDLC and Async mode) High Z High Z PCM Transmit Data Port 1 LNC Transmit Serial Data Port 3 (HDLC and Async mode) Pin Symbol In (I) During No. Out (O) Reset 74 RxD2 / LCxD2/ LCTS2 I I I 82 TxD2 / LCLK2 O I/O 81 TSC2 O 75 RxD1 / LRxD3 I I O O(OD) 80 TxD1 / LTxD3 Data Sheet 32 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 14 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) (cont'd) After Reset Function PCM Tristate Control Port 1 Supplies a control signal for an external driver ('low' when the corresponding TxDoutput is valid). LNC3 Tristate Control / Request to Send 2 modes per S/W selectable: 1) TxD output is valid (HDLC mode). Supplies a control signal for an external driver. ('low' when the corresponding TxDoutput is valid). 2) 'request-to-send' functionality (Async mode) PCM Receive Data Port 3 LNC3 Collision Data 2 modes per S/W selectable: 1) Collision Data (HDLC Mode). 2) 'clear-to-send' functionality (Async mode) weak low weak low PCM Transmit Data Port 3 LNC External Clock Port 3 When configured as output may be driven at the following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz TEST(1) H strap refer to Page 38 PCM Tristate Control Port 3 Supplies a control signal for an external driver ('low' when the corresponding TxD output is valid). Pin Symbol In (I) During No. Out (O) Reset 79 TSC1 / O LTSC3/ LRTS3 H PLL PowerDown strap pull-up refer to Page 38 71 RxD3 / LCxD3/ LCTS3 I I I I 86 TxD3 / LCLK3 O I/O 83 TSC3 O . Data Sheet 33 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 15 Pin No. 94 95 1 Clock Generator Pins (DELIC-PB) (Additionally to IOM/PCM Clocks) In (I) During After Function Out (O) Reset Reset I O I I O I I O I 16.384 MHz External Crystal Input 16.384 MHz External Crystal Output DCXO Power Down and Bypass Activating this input powers down the on-chip DCXO PLL. The input CLK16-XI is used directly as the internal 16.384 MHz clock, and the oscillator and the shaper are bypassed. Required for testing; during normal operation this input should be permanently low (`0'). External DSP Clock Provides a DSP clock other than 61.44 MHz from an external oscillator. DSP Operational Frequency Selection (e.g. for test purpose) 0: The DSP is clocked internally at 61.44 MHz 1: The DSP clock is driven by the CLK_DSP input pin Layer-1 Clock 15.36 MHz or 7.68 MHz General Purpose Clock Output 2.048 MHz, 4.096 MHz, 8.192 MHz, 15.36 MHz or 16.384 MHz External Reference Clock Synchronization input from Layer-1 ICs (8 kHz, 512 kHz or 1.536 MHz) This pin is connected to the VIP's REFCLK output at 1.536 MHz. Reference Clock Input: Synchronization of DELIC clock system Output: Used to drive a fraction of XCLK to the system clock master (8 kHz or 512 kHz programmable) Symbol CLK16-XI CLK16-XO DCXOPD 2 CLK_DSP I I I 3 DSP_FRQ I I I 48 28 L1_CLK CLKOUT O O O O O O 4 XCLK I I I 90 REFCLK I/O I I Data Sheet 34 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 16 Pin No. 8 19 26 36 46 49 57 65 72 84 91 9 20 27 37 47 58 66 73 85 92 96 99 100 93 97 98 Power Supply Pins (DELIC-PB) In (I) During After Out (O) Reset Reset I I I Function Power Supply 3.3 V Used for core logic and interfaces in pure 3.3 V environment Symbol VDD VSS I I I Digital Ground (0 V) VDDA I I I Power Supply 3.3 V Analog Logic Used for DCXO and PLL Analog Ground Used for DCXO and PLL VSSA I I I Data Sheet 35 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 17 Pin Symbol No. 54 JTCK JTAG and Emulation Interface Pins (DELIC-PB) In (I) During After Out (O) Reset Reset I I I Function Used for boundary scan according to IEEE 1149.1 JTAG Test Clock Provides the clock for JTAG test logic. Used also for serial emulation interface. Test Mode Select A '0' to '1' transition on this pin is required to step through the TAP controller state machine. Test Data Input In the appropriate TAP controller state test data or a instruction is shifted in via this line. Used also for serial emulation interface. This pin must not be driven to low on the board and should be connected to a pull-up during reset and operation to ensure functioning of DELIC SCAN Enable When both SCANMO and SCANEN are asserted, the full-scan tests of DELIC are activated. Not used during normal operation. Test Data Output In the appropriate TAP controller state test data or an instruction is shifted out via this line. Used also for serial emulation interface. Test Reset Provides an asynchronous reset to the TAP controller state machine. DSP Stop Pin Stops external logic during breakpoints. Activated when a stop to the DSP is issued. 53 TMS I I I 52 TDI / I I I SCANEN 51 TDO O O O 55 TRST I I I 63 DSP_STOP O BOOT O Strap (pulldown) refer to Table 19 36 Data Sheet 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 18 Pin No. 50 Test Interface Pins (DELIC-PB) In (I) During Out (O) Reset I I After Reset I Function Scan Mode If driven to '1' during device tests, TDI input is used as enable for full scan tests of the DELIC. SCANMO should be tied to GND during normal operation. Symbol SCANMO Data Sheet 37 2003-07-31 PEB 20570 PEB 20571 Pin Description 2.5 Table 19 Pin No. DREQR (11) Strap Pin Definitions Strap Pins (Evaluated During Reset) Strap Name Strap Function CLOCK MASTER 0: (default) Clock Slave PDC and PFS are used as inputs. PDC = 2.048 MHz PFS = 4 kHz 1: Clock Master PDC and PFS are used as outputs. PDC = 2.048 MHz PFS = 8 kHz DSP_STOP BOOT (63) 0: (default) The DSP starts running from address FFFEH, and executes the P boot routine. 1: The DSP starts running directly from address 0000H. The boot routine is not executed. Regular Work Mode DCL (40): TSC3 (83): TSC2 (81) TEST(2) TEST(1) TEST(0) 111: (default) 101 100 011 010 001 110 Test mode 1 Test mode 2 Test mode 3 Test mode 4 Test mode 5 undefined DREQT (10) EMULATION 0: (default) After reset the boot-routine loads the program BOOT RAM via the P-interface (via the general mail-box). 1: After reset the boot-routine loads the program RAM via the CDI mail-box (via the JTAG interface). Data Sheet 38 2003-07-31 PEB 20570 PEB 20571 Pin Description Table 19 LTSC (60) Strap Pins (Evaluated During Reset) (cont'd) PLL BYPASS 0: DSP_CLK input pin (the DSP fall-back clock) is used as source for the 61 MHz clock division chain. (Only for testing). 1: (default) The PLL output is used as the source for the 61 MHz clock division chain. TSC1 (79) TSC0 (77) PLL POWER 0: The PLL is powered-down. (for IDDQ tests) DOWN 1:(default) The PLL is on. RESET COUNTER BYPASS 0: The reset-counter is bypassed, thus the internal reset is the filtered reset. The internal reset lasts 1-2 16 MHz cycles after a deactivation of RESET. 1: (default) The internal reset lasts 4-5 8 kHz cycles (> 500 s) after a deactivation of RESET Note: When the strap pins are not driven externally during reset, they are driven by internal pull-ups/pull-downs. To reduce power consumption, the internal pull-up/ pull-down resistors are connected only during activated RESET input. To ensure the default value of the straps, the pins must not be driven during reset. In case of fixed external pull-up/pull-down, a pull-up/pull-down resistance of 10 K +/-10% is recommended. Note: Because of the internal pull-ups are too weak its recommended to connect any pin used as a strap during reset, to an external pull-up/ pull-down resistor, even if it's supposed to be driven to it's default strap-value. Data Sheet 39 2003-07-31 PEB 20570 PEB 20571 Interface Description 3 3.1 Interface Description Overview of Interfaces The DELIC provides the following system interfaces: IOM-2000 Interface A new serial layer 1 interface driving up to three VIP/ VIP8 (Versatile ISDN Port, PEB 20590/ PEB 20591). Each VIP provides eight 2B+D ISDN channels, which can be programmed via IOM-2000 to S/T mode or UPN mode. IOM-2 (GCI) Interface Two standard IOM-2 (GCI) ports with eight 2B+D ISDN channels each, at a data rate of up to 2 x 2.048 Mbit/s. They can be combined to a 4.096 Mbit/s highway. PCM Interface Four standard Master/Slave PCM interfaces with up to 32 time slots each, at a data rate of up to 4 x 2.048 Mbit/s. They can be combined to two 4.096 Mbit/s highways or one 8.192 Mbit/s highway. Additionally, 128 time slots of 256 time slots per 8 kHz frame can be transmitted at a rate of 16.384 Mbit/s. Serial Communication Interface (GHDLC) An asynchronous serial port supporting HDLC formatted data frames at a data rate of up to 8.192 Mbit/s. Microprocessor Interface A standard 8-bit multiplexed/de-multiplexed P interface, compatible to Intel/Infineon (e.g. 80386EX, C166) and Motorola (e.g. 68340, 801) bus systems. It includes two separate mailboxes, one for normal data transfer, and one for fast DMA transfers. JTAG Boundary Scan Test Interface * DELIC provides a standard test interface according to IEEE 1149.1. The 4-bit TAP controller has an own reset input. * The JTAG pins TDI, TDO and JTCK may also be used as interface for DSP emulation. Data Sheet 40 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.2 3.2.1 IOM-2000 Interface Overview The IOM-2000 interface represents a new concept for connecting ISDN layer-1 devices to the DELIC. The transceiver unit (TRANSIU) and the DSP perform the layer-1 protocol, which enables flexible and efficient operation of the transceiver IC (VIP/ VIP8). VIP/ VIP8 supports two types of ISDN interfaces: 2-wire (ping-pong) UPN interfaces and 4-wire S/T interfaces. For detailed description please refer to VIP/ VIP8 Data Sheet. The IOM-2000 interface consists of the following signals: * Frame Synchronization: IOM-2000 uses the same 8 kHz FSC as the IOM-2 ports. * Data Interface: Data is transmitted via DX line from DELIC to VIP with DCL_2000 rising edge. Data is received via DR line from VIP to DELIC, sampled with DCL_2000 falling edge. * Command/Status Interface: Configuration and control information of VIP's layer-1 transceivers is exchanged via CMD and STAT lines. * Data/Command Clock: Data and commands for one VIP are transmitted at 3.072 MHz. When DELIC drives 2 or 3 VIPs, the transmission rate is increased. * Reference Clock: In LT-T mode, the VIP provides a reference clock synchronized to the exchange. In LT-S or UPN mode, DELIC is always the clock master to VIP. bit 1 bit 0 data ctrl bit 0 data Data Transmit / Receive in S/T mode f=3.072 MHz (2 x 8 x 192 kbit/s) Data Transmit / Receive for UPN mode f=3.072 MHz (8 x 384 kbit/s) FSC Channel_0 DCL_2000 DX DR STAT CMD DELIC PEB 20570 (PEB 20571) S/T: DX / DR: UPN: . . . Channel_7 VIP PEB 20590 (PEB 20591) Figure 11 Data Sheet Overview of IOM-2000 Interface Structure (Example with One VIP) 41 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.2.2 3.2.2.1 IOM-2000 Frame Structure Data Interface On the ISDN line side of the VIP, data is ternary coded. Since the VIP contains logic to detect the level of the signal, only the data value is transferred via IOM-2000 to DELIC. UPN Mode In UPN mode, only data is sent via the IOM-2000 data interface. S/T Mode In S/T mode, data and control information is sent via IOM-2000 data interface. Every data bit has a control bit associated with it. Thus, for each S/T line signal, 2 bits are transferred via DX and DR. Bit0 is assigned to the user data, and bit1 carries control information. Table 20 0 0 1 1 0 1 0 1 Control Bits in S/T Mode on DR Line Logical '0' received on line interface Logical '1' received on line interface Received E-bit = inverted transmitted D-bit (E=D) (LT-T only) F-bit (Framing) received; indicates the start of the S frame ctrl (bit1) data (bit0) Function Table 21 0 0 1 1 0 1 0 1 Control Bits in S/T Mode on DX Line Logical '0' transmitted on line interface Logical '1' transmitted on line interface not used F-bit (Framing) transmitted; indicates the start of the S frame ctrl (bit1) data (bit0) Function Note: 'data' is always transmitted prior to 'ctrl' via DX/DR lines (refer to Figure 12). Data Sheet 42 2003-07-31 PEB 20570 PEB 20571 Interface Description FSC DCL F-bit 125 s 3.072 MHz data ctrl Ch0 bit0 Ch1 bit0 (data) Ch2 bit0 DX/DR Ch7 bit0 (data) Ch0 bit1 Ch1 bit0 (ctrl) Ch2 bit1 Ch7 bit0 (ctrl) Ch0 bit2 Ch1 bit1 (data) Ch2 bit2 Ch7 bit1 (data) LT-S mode: UPN mode: data Ch1,3,5,7 in S mode (LT-S) Ch0,2,4,6 in UPN mode last bit of UPN frame last bit of LT-S frame Ch6 bit37 Ch7 bit 23 (ctrl) Figure 12 IOM-2000 Data Sequence (1 VIP with 8 Channels) Note: 1. Data transfer on IOM-2000 interface always starts with the MSB (related to B channels), whereas CMD and STAT bits transfer always starts with LSB (bit 0) of any register 2. All registers follow the Intel structure (LSB=20, MSB=231) 3. Unused bits are don't care ('x') 4. The order of reception or transmission of each VIP channel is always channel 0 to channel 7. A freely programmable channel assignment of multiple VIPs on IOM-2000 (e.g., ch0 of VIP_0, ch1 of VIP_0, ch0 of VIP_1, ch2 of VIP_0,...) is not possible. Data Sheet 43 2003-07-31 PEB 20570 PEB 20571 Interface Description FSC DCL F-bit Ch0 bit0 Ch23 bit0 Ch24 bit0 DX/DR 125 s 12.288 MHz not used (don't care) Ch31 bit0 Ch0 bit1 Ch23 bit1 Ch24 bit1 not used (don't care) Ch31 bit1 Ch0 bit37 (example for 24 channels in UPN mode) Ch23 bit37 Ch24 bit37 Ch31 bit37 not used Figure 13 IOM-2000 Data Order (3 VIPs with 24 Channels) Receive Data Channel Shift In receive direction (DR), data of all IOM-2000 channels (ch0...7 if one VIP is used, ch0 ... ch23 if three VIPs are used) is shifted by 2 channels with respect to the transmitted data channels (DX), assuming a start of transmission of ch0 bit0 with the FSC signal. DELIC is transmitting ch0, while receiving ch2 via DR the same time, etc. DX DR ch0 ch2 ch1 ch3 ch2 ch4 ch3 ch5 ch4 ch6 ch5 ch7 ch6 ch0 ch7 ch1 ch0 ch2 Data Sheet 44 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.2.2.2 Command and Status Interface The CMD and STAT lines are the configuration and control interface between DELIC and VIP. The bit streams are partitioned into 32-bit words carrying information dedicated to the VIPs (CMD_0 / STAT_0) followed by information dedicated to the individual channels of the same VIP (CMD_0_0 ... CMD_2_7 or STAT_0_0 ... STAT_2_7). Note: As opposed to data, command and status bits are sent channel-wise, starting with channel_0. The transmission clock is the same as the DR/DX data clock. FSC DCL CMD C_0 125 s 3.072 MHz 3x32-bit empty C_0C0 C_0C1 C_0C2 C_0C3 C_0C4 C_0C5 C_0C6 C_0C7 31 0 1 2 31 C_0 ... 012 Command bits to VIP_0 Commands bits to VIP_0 channel_7 3x32-bit empty S_0 S_0C0 S_0C1 S_0C2 S_0C3 S_0C4 S_0C5 S_0C6 S_0C7 S_0 ... 0 1 2 31 0 1 2 31 STAT Status bits of VIP_0 Status bits of VIP_0 channel_7 Note: C_0 refers to CMD_0, S_0 to STAT_0 C_0C0 refers to CMD_0_0, S_0C0 to STAT_0_0 Figure 14 IOM-2000 CMD/STAT Handling (1 VIP with 8 Channels) Note: The position of each VIP within the IOM-2000 frame is programmable by two VIP pins (VIP_ADR0, VIP_ADR1) to IOM-2000 channels 0..7, 8..15 or 16..23. FSC 3 empty 32-bit words VIP_0 VIP_1 125 s 3 empty 32-bit words VIP_2 3 empty 32-bit words VIP_0 ... VIP_0 ch0 ch7 VIP_1 ch0 ch7 VIP_2 ch0 ch7 reserved CMD / STAT Figure 15 Data Sheet IOM-2000 Command/Status Sequence (3 VIPs with 24 Channels) 45 2003-07-31 PEB 20570 PEB 20571 Interface Description Commands to VIP_n (CMD_n, n = 0 ... 2) Initialization and control information for each VIP is sent by DELIC in the following sequence every 125 s via the IOM-2000 CMD line (32 CMD_n bits per VIP_n): Note: All bits are programmed in VIP Command register (VIPCMR0..2). 31 x 23 x 15 x 7 CMD_n DELCH(2:0) EXREF REFSEL(2:0) x x x RD_n PLLPPS SH_FSC x x x x x x 8 DELRE 0 WR_n x x x x x x 16 x 24 x Commands to VIP_n, Channel_m (CMD_n_m, m = 0 ... 7) Initialization and control information for each VIP channel is sent by DELIC in the following sequence every 125 s via the IOM-2000 CMD line (32 CMD_n_m bits per VIP_n Channel_m): Note: All bits except WR_ST, SMINI(2:0) and MSYNC are programmed in TRANSIU Initialization Channel Command register (TICCR); bits WR_ST, SMINI(2:0) and MSYNC reside in the TRANSIU Tx data RAM. 31 CMD_n_m 23 x 15 AAC(1:0) 7 MODE(2:0) Data Sheet 24 FIL SMINI(2:0) MSYNC EXLP PLLS 16 DHEN x x PDOWN LOOP TX_EN PLLINT 8 BBC(1:0) OWIN(2:0) MF_EN 0 MOSEL(1:0) 46 PD WR_ST RD WR 2003-07-31 PEB 20570 PEB 20571 Interface Description Status from VIP_n (n = 0 ... 2) Status information is sent by each VIP in the following sequence via the STAT line (32 STAT_n bits per VIP_n): 31 STAT_n 23 x 15 x 7 DELAY(7:0) Note: Bits DELAY are read from VIP Status register (VIPSTR) in TRANSIU. x = unused Status from VIP_n, Channel_m (m = 0 ... 7) Status information is sent by each VIP channel in the following sequence via the STAT line (32 STAT_n_m bits per VIP_n Channel_m): 31 STAT_n_m 23 x 15 x 7 x MSYNC* FCV* FSYNC* SLIP FECV x x x x x x 0 RxSTA(1:0) x x x x x x 8 x x x x x x x x 16 x 24 x x x x x x x 0 x x x x x x 8 x x x x x x x x 16 x 24 x Note: Marked bits (*) are not evaluated by the DELIC, only for VIP testing. Bits SLIP, FECV and are directly accessible in the TRANSIU receive data RAM. x = unused Data Sheet 47 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.2.3 3.2.3.1 UPN State Machine INFO Structure on the UPN Interface Signals controlling and indicating the internal state of all UPN transceiver state machines are called INFOs. Four different INFOs (INFO 0, 1W, 1, 2, 3, 4) may be sent over the UPN interface, depending on the actual state (Synchronized, Activated, Pending Activation,...). When the line is deactivated, INFO 0 (=no signal on the line) is exchanged by the UPN transceivers at either end of the line. When the line is activated, INFO 3 (in upstream direction) and INFO 4 (in downstream direction) are continuously sent. INFO 3 and 4 contain the transmitted data (B1, B2, D, M). INFO 1/2 are used for activation and synchronization. Table 22 Name INFO 0 INFO 1W INFO Structure on UPN Interface Direction Description Upstream No signal on the line Downstream Upstream Asynchronous Wake Signal 2 kHz burst rate F0001000100010001000101010100010111111 Code violation in the framing bit 4 kHz burst rate F000100010001000100010101010001011111M1)DC Code violation in the framing bit INFO 1 Upstream INFO 2 Downstream 4 kHz burst rate F000100010001000100010101010001011111M1) Code violation in the frame bit Upstream 4 kHz burst rate No code violation in the framing bit User data in B, D and M channels B channels scrambled, DC bit2) optional INFO 3 INFO 4 Downstream 4 kHz burst rate No code violation in the framing bit User data in B, D and M channels B channels scrambled, DC bit2) optional Data Sheet 48 2003-07-31 PEB 20570 PEB 20571 Interface Description Note: 1)The M channel superframe contains: CV code violation [1 kbit/s (once in every fourth frame)] S bits transparent[1 kbit/s channel] T bits transparent[2 kbit/s channel] 2)DC balancing bit; F = Framing bit Data Sheet 49 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.2.3.2 UPN Mode State Diagram TM1 TM2 RESET TIM TIM RES Test M ode it1 it2 TIM DR DR TM1 TM2 DC * DR Reset i0 * RES P e n d . D e a c t. i0 i0 i0 DI ARx DR G 4 W a it for D R i0 i0 DC DI ARx DC D e a c tiva te d i0 DR i0 i1w AR DC ARx DR P en d . A c t. i2 i1w i1 Note: TM2 = Send Continuous Pulses TM1 = Send Single Pulses it1 = test signal invoked by TM1 it2 = test signal invoked by TM2 ARx = AR, AR2 Uncond. Transitions by: RES, TM1, TM2, DR UAI DC ARx, AI DR S y n ch ro n iz e d i1 RSY DC ARx i1, i3 DR i4 i3 i1 P interface OUT IN R e s y nc h ro n. i2 i1 Ind. Cmd. S ta te AI i3 DC ARx, AI DR Upn interface DELPHI UP SM.vsd ix iy A ctiv a te d i4 i3 Figure 16 Data Sheet UPN State Diagram 50 2003-07-31 PEB 20570 PEB 20571 Interface Description The UPN state machine has unconditional and conditional states (refer to Figure 16): Unconditional States Reset This state is entered unconditionally after a low appears on the RESET pin or after the receipt of command RES (software reset). The analog transceiver part is disabled (transmission of INFO 0) and the UPN interface awake detector is inactive. Hence, activation from terminal (TE) is not possible. Test Mode The test signal (iti) sent to the UPN interface in this state is dependant on the command which originally invoked the state. TM1 causes single alternating pulses to be transmitted (it1); TM2 causes continuous alternating pulses to be transmitted (it2). The burst mode technique normally employed on the UPN interface is suspended in this state and the test signals are transmitted continuously. Pending Deactivation To access any of the conditional states from any of the above unconditional states, the pending deactivation state must be entered. This occurs after the receipt of a DR command. In this state the awake detector is activated and the state is left only when the line has settled (i.e., INFO 0 has been detected for 2 ms) or by the command DC. Note: Although DR is shown as a normal command, it may be seen as an unconditional command. No matter which state the LT is in, the reception of a DR command will always result in the pending deactivation state being entered. Conditional States Wait for DR This state is entered from the pending deactivation state once INFO 0 or DC has been identified. From here the line may be either activated, deactivated or a test loop may be entered. Deactivated This is the power down state of the physical protocol. The awake detection is active and the device will respond to an INFO 1w (wake signal) by initiating activation. Data Sheet 51 2003-07-31 PEB 20570 PEB 20571 Interface Description Pending Activation This state results from a request for activation of the line, either from the terminal (INFO 1w) or from the layer-2 device (AR, AR2). INFO 2 is then transmitted and the DSP waits for the responding INFO 1 from the remote device. Synchronized This state is reached after synchronization upon the receipt of INFO 1, i.e. after a maximum of 10 ms. In this state, INFO 2 is supplied to the remote terminal for synchronization. Activated Info 1 has a code violation in the framing bit (F-bit), whereas INFO 3 has none. Upon the reception of two frames without a code violation in the F bit, the activated state is entered and INFO 4 is transmitted. The line is now activated; INFO 4 is sent to the remote and INFO 3 is received from the remote. Re-synchronization If the recognition of INFO 3 fails, the receiver will attempt to resynchronize. Upon entering this state, INFO 2 is transmitted. This is similar to the original synchronization procedure in the pending activation state (the indication given to layer 2 is different). However, as before, recognition of INFO 1 leads to the synchronized state. Table 23 Command Deactivate request Reset Test mode 1 Test mode 2 Activate request UPN State Machine Codes Abbr. DR RES TM1 TM2 AR Code 0000 0001 0010 0011 1000 1010 Remark Initiates a complete deactivation from the exchange side by transmitting INFO 0 (x) (x) Transmission of pseudo-ternary pulses at 2 kHz frequency (x) Transmission of pseudo-ternary pulses at 192 kHz frequency (x) Used to start an exchange initiated activation Transmission of INFO 2, switching of loop 2 (at TE), T bit set to one Activate request test AR2 loop 2 Data Sheet 52 2003-07-31 PEB 20570 PEB 20571 Interface Description Table 23 Command UPN State Machine Codes (cont'd) Abbr. Code 1100 1111 Remark Transmission of INFO 4, T bit set to zero Deactivation acknowledgement, quiescent state Activate indication = AI "blocked" Deactivate confirmation DC (x) unconditional commands Note: The UPN state machine does support loops but neither C/I commands (ARL) nor Indications are provided by the mailbox protocol. An loop can be programmed by setting bits TICCMR:LOOP and TICCMR:EXLP for defining it is an internally or externally loop. Indication Timing Resynchronizing Activate request U only activation indication Activate indication Abbr. TIM RSY AR UAI AI Code 0000 0100 1000 0111 1100 1111 Remark Deactivate state, activation from the line not possible Receiver is not synchronous INFO 1w received INFO 1 received, synchronous receiver Receiver synchronous, i.e., activation completed INFO 0 or DC received after deactivation request Deactivate indication DI Data Sheet 53 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.2.4 S/T State Machine A finite state machine in the DELIC controls the VIP S/T line activation/deactivation procedures and transmission of special pulse patterns. Such actions can be initiated by primitives (INFOs) on the S/T interface or by C/I codes sent via the mailbox. Depending on the application mode and the transfer direction, the S/T state machines support different codes in conditional and unconditional states: LT-S mode Codes: States: data downstream = Commands: reset, test mode, activate req,.. data upstream = Indications: not sync, code violation, timer out,.. deactivated, activated, pending, lost framing, test mode The state diagram is shown in Figure 17. LT-T mode data upstream = Commands: reset, test, activate request,.. data downstream = Indications: command x acknowledged,.. Conditional states: power up, pending deactivation, synchronized, slip detected,.. The state diagram is shown in Figure 18. Unconditional states may be entered from any conditional state and should be left with the command TIM: test mode, reset state,.. The S/T layer-1 activation and deactivation procedures implemented in the DELIC are similar to the ones implemented in the PEB 2084, QUAT-S. Codes Data Sheet 54 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.2.4.1 Table 24 Command LT-S Mode LT-S State Machine Codes Abbr. DR RES TM1 TM2 AR DC Code 0000 0001 0010 0011 1000 1111 Remark Initiates a complete deactivation from the exchange side by transmitting INFO 0 (x) (x) Transmission of pseudo-ternary pulses at 2 kHz frequency (x) Transmission of pseudo-ternary pulses at 96 kHz frequency (x) Used to start an exchange initiated activation Deactivation acknowledgement, quiescent state Deactivate request Reset Test mode 1 Test mode 2 Activate request Deactivate confirmation (x) unconditional commands Note: The LT-S state machine does not support loops. So neither C/I commands nor Indications are provided by the mailbox protocol. A loop can be programmed by setting bits TICCMR:LOOP and TICCMR:EXLP for the respective channel. Indication Timing Resynchronizing Activate request Code violation received Abbr. TIM RSY AR CVR Code 0000 0100 1000 1011 Receiver is not synchronous INFO 0 received After each multi-frame the reception of at least one illegal code violation is indicated four times Receiver synchronous, i.e., activation completed Timer (32 ms) expired or INFO 0 received after deactivation request Remark Activate indication Deactivate indication AI DI 1100 1111 Data Sheet 55 2003-07-31 PEB 20570 PEB 20571 Interface Description RESET SCP SSP TIM RES DR TIM DR DR TIM R e se t i0 * DC G 4 P e n d. D ea c t. i0 ARD1) i0 Test M ode it1 it2 DC * SCP SSP Any State RES Any State i0 or 32ms DI DR G 4 W a it fo r D R ARD1) i0 * DC DI DC DR G 1 D e a ctiv ate d ARD1) i0 i0 i0 AR DC AR DR G 2 P e n d . A ct. i2 i3 Note: i3 TM2 = Send Continuous Pulses TM1 = Send Single Pulses it1 = test signal invoked by TM1 it2 = test signal invoked by TM2 DR AI DC AR G 3 A c tiv a te d i4 i3 OUT P interface DR IN i3 i3 DC AR RSY Ind. Cmd. G 2 L o st F ra m in g i2 DELPHI LT-S SM.vsd S ta te S interface ix iy i3 Figure 17 Data Sheet State Diagram of LT-S Mode 56 2003-07-31 PEB 20570 PEB 20571 Interface Description LT-S Mode States * G1 deactivated The line interface is not transmitting. There is no signal detected on the S interface, and no activation command is received. * G2 pending activation As a result of an INFO 1 detected on the S line or an AR command, the line interface begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise reception of INFO 3 is to be implemented in software. In case of an ARL command, loop 2 is closed. * G3 activated Normal state where INFO 4 is transmitted to the S interface. The line interface remains in this state as long as neither a deactivation nor a test mode is requested, and the receiver does not loose synchronism. When receiver synchronism is lost, INFO 2 is sent automatically. After reception of INFO 3, the transmitter continues sending INFO 4. * G2 lost framing This state is reached when the line interface has lost synchronism in the state G3 activated. * G4 pending deactivation This state is triggered by a deactivation request DR. It is an unstable state: status DI (state "G4 wait for DR") is issued by the DELIC when either INFO 0 is received, or an internal timer of 32 ms expires. * G4 wait for DR Final state after a deactivation request. The line interface remains in this state until a response to DI (in other words DC) is issued. * Test mode 1 Single alternating pulses are sent on the S interface (2 kHz repetition rate). * Test mode 2 Continuous alternating pulses are sent on the S interface (96 kHz). Data Sheet 57 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.2.4.2 Table 25 Command LT-T Mode LT-T Mode State Machine Codes (Conditional States) Abbr. Code TIM RES TM1 0000 0001 0010 Remark Requests the line interface to change into power-up state Reset of state machine. Transmission of Info 0. No reaction to incoming infos (x) Transmission of single pulses on the S/Tinterface. The pulses are transmitted with alternating polarity at a frequency of 2 kHz. (x) Transmission of continuous pulses on the S/T-interface. The pulses are sent with alternating polarity at a rate of 96 kHz. TM2 is an unconditional command (x). Activation Request with priority 8 for Dchannel transmission. This command is used to start a LT-T initiated activation. Dchannel priority 8 is the highest priority. It should be used to request signaling information transfer. Activation request with priority 10 for Dchannel transmission. This command is used to start a LT-T initiated activation. Dchannel priority 10 is a lower priority. It should be used to request packet data transfer. Activation of loop 3 (x) This command forces the line interface into "F3 power down" mode. Timing Request Reset Test mode 1 Test mode 2 TM2 0011 Activate request, priority 8 AR8 1000 Activate request, priority 10 AR10 1001 Activate request loop Deactivate indication ARL DI 1010 1111 (x) unconditional commands Data Sheet 58 2003-07-31 PEB 20570 PEB 20571 Interface Description Indication Deactivate request Reset Test mode 1 Test mode 2 Slip detected Abbr. Code DR RES TM1 TM2 SLIP 0000 0001 0010 0011 0011 0100 0111 1000 1010 1011 Remark Deactivation request if left from F7/F8 Reset acknowledge TM1 acknowledge TM2 acknowledge Frame wander larger than +/- 25 s Signal received, receiver not synchronous Line interface is powered up INFO 2 received Loop 3 closed After each multiframe the reception of at least one illegal code violation is indicated four times. Loop 3 activated INFO 4 received, D-channel priority is 8 or 9 INFO 4 received, D-channel priority is 10 or 11 Line interface is powered down Re-synchronization during RSY level detect Power up Activate request Activate request loop Code violation received PU AR ARL CVR Activate indication loop Activate indication with priority class 8 Activate indication with priority class 10 Deactivate confirmation AIL AI8 AI10 DC 1110 1100 1101 1111 Data Sheet 59 2003-07-31 PEB 20570 PEB 20571 Interface Description DC i4 DI TIM F3 Power Down i0 AR i2 i0 PU AR2) F4 Pending Act. i1 i0 i0 DI DI AR PU TIM TIM F3 Power Up i0 i2 i0 i4 RSY i4 X TIM RES TMI4) TMI4) DI Test Mode i it5) * TIM F5 Unsynchronized DI i0 ix i2 TMI4) Any State RES AR X RES ix i2 i4 i2 ix AI3) AR2) F7 Activated i3 i4 i0*TO1 i4 DR1) X F3 Pending Deact. i0 i0 RSY X DI TIM i0*TO1 i2 DI (from F7, F8) DI RES TIM RESET i0 * F6 Synchronized i3 i2 i4 DELIC RESET pin F8 Lost Framing i0 i0 TIM (from F7, F8) 1) 2) DR for transition from F7 or F8 AR stands for AR8 or AR10 3) AI stands for AI8 or AI10 4) TMI stands for TM1 or TM2 5) it1 = test signal invoked by it1 TO1: 16 ms Figure 18 Data Sheet LT-T Mode State Diagram (Conditional and Unconditional States) 60 2003-07-31 PEB 20570 PEB 20571 Interface Description LT-T Mode (Conditional States) * F3 power down This is the deactivated state of the physical protocol. The receive line awake unit is active. * F3 power up This state is similar to "F3 power down". The state is invoked by a Command TIM = "0000" (or DI static low). * F3 pending deactivation The line interface reaches this state after receiving INFO 0 (from states F5 to F8). From this state an activation is only possible from the line (transition "F3 pending deactivation" to "F5 unsynchronized"). The power down state may be reached only after receiving DI. * F4 pending activation Activation has been requested from the terminal; INFO 1 is transmitted; INFO 0 is still received; "Power Up" is transmitted in the C/I channel. This state is stable: timer T3 (ITU I.430) is to be implemented in software. * F5/8 unsynchronized At the reception of any signal the VIP ceases to transmit INFO 1, adapts its receiver circuit, and awaits identification of INFO 2 or INFO 4. This state is also reached after the line interface has lost synchronism in the states F6 or F7 respectively. * F6 synchronized When the VIP receives an activation signal (INFO 2), it responds with INFO 3 and waits for normal frames (INFO 4). * F7 activated This is the normal active state with the layer 1 protocol activated in both directions. From state "F6 synchronized", state F7 is reached almost 0.5 ms after reception of INFO 4. * F7 slip detected When a slip is detected between the T interface clocking system and the IOM-2 interface clocks (phase wander of more than 25 s, data may be disturbed) the line interface enters this state, synchronizing again the internal buffer. After 0.5 ms this state is relinguished. Data Sheet 61 2003-07-31 PEB 20570 PEB 20571 Interface Description LT-T Mode (Unconditional States) The unconditional states should be left with the command TIM. * Test mode 1 Single alternating pulses are sent on the T interface (2 kHz repetition rate). * Test mode 2 Continuous alternating pulses are sent on the T interface (120 kHz). * Reset state A hardware or software reset (RES) forces the line interface to an idle state where the analog components are disabled (transmission of INFO 0) and the T line awake detector is inactive. Restriction in LT-T Mode The two first TRANSIU Channels out of 24, (i.e. Channel_0 and channel_1 in the IOM2000 frame, referring to VIP_0, ch_0 and ch_1) do not work in LT-T mode. In order to have an optimized usage of the LT-channels it is recommended to proceed as follows: * If only one VIP is used, 8 channels can be applied in LT-T mode by using a DCL_2000 clock of 6.144 MHz and mapping the VIP to channel 8..15. * If 2 VIPs are used, up to 16 channels can be applied in LT-T mode by using a DCL_2000 of 12.288 MHz and mapping the VIPs to channel 8..23. * If 3 VIPs are used up to 22 channels (channel 2..23) may be applied in LT-T mode by using a DCL_2000 of 12.288 MHz. Data Sheet 62 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.3 IOM(R)-2 Interface IOM-2 is a standardized interface for interchip communication in ISDN line cards for digital exchange systems developed by ALCATEL, Siemens, Plessey and ITALTEL. The IOM-2 interface is a four-wire interface with a bit clock, a frame clock and one data line per direction. It has a flexible data clock. This way, data transmission requirements are optimized for different applications. Figure 19 IOM(R)-2 Interface in Digital Line Card Mode Note: In Laundered mode, 8 identical IOM-2 subchannels are provided. In analog Line cards, a 6-bit C/I Channel is available for signaling information. In digital Line cards, a dedicated 2-bit D-channel carries the signaling information. 3.3.1 FSC DCL DD DU B1, B2 MONITOR D C/I MR MX Signals / Channels Frame Synchronization Clock, 8 kHz Data Clock, up to 4.096 MHz *) Data Downstream, up to 4.096 Mbit/s *) Data Upstream, up to 4.096 Mbit/s *) User data channels, 64 kbit/s each Monitor Channel Signaling Channel, 16 kbit/s Command/Indication Channel Monitor Receive handshake signal Monitor Transmit handshake signal *) For detailed clock and data rates, refer to IOMU feature description in Chapter 4.3.2 Data Sheet 63 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.4 P Interface The P interface may be operated in different modes. This chapter describes how to configure the DELIC to each mode. 3.4.1 Intel/Infineon or Motorola Mode The processor mode is selected by the MODE input pin of the DELIC. "Low" level selects Infineon/ INTEL mode, "HIGH" level selects Motorola mode. 3.4.2 De-Multiplexed or Multiplexed Mode In both modes, the A-bus and the D-bus are used in parallel. The A-bus should be connected to the 8 LSBs of AD-bus, coming from the P, also in multiplexed mode. The mode is determined according to the ALE input pin. When ALE is permanently driven to `1', the DELIC works in de-multiplexed mode. Otherwise the DELIC works in multiplexed mode. The next figure describes the connection of the DELIC to the address and data buses in the different modes. Note: Motorola mode is used only with de-multiplexed AD bus. Intel/Infineon mode may be used with both, multiplexed or de-multiplexed AD bus. Data Sheet 64 2003-07-31 PEB 20570 PEB 20571 Interface Description Multiplexed Mode P AD 7 8 D A ALE ALE DELIC LATCH De-multiplexed Mode P D 7 A ALE `1' 8 D A DELIC LATCH Figure 20 DELIC in Multiplexed and in De-Multiplexed Bus Mode Note: In both modes only the 7 LSBs of A-bus or AD/bus are connected to the Address inputs of the DELIC. In DMA mode DACK/A4 input pin is used as DACK, and A4 is internally driven to `0'. In this case A4 of the P A/AD-bus is also not connected to the DELIC. Data Sheet 65 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.4.3 DMA or Non-DMA Mode The internal interface between the on-chip DSP and P is established by two Mailboxes: a 'general' Mailbox and a dedicated DMA Mailbox. The non-DMA mode provides the option to combine them together building a double-sized 'general' Mailbox. The DELIC is configured to DMA or non-DMA mode by a dedicated bit in the P interface configuration register (MCFG:DMA). DMA Mode The DMA Mailbox can be accessed only by a DMA controller. The DACK input pin (together with the RD and WR signals) is used to access the DMA Mailbox. Only the general Mailbox can be accessed directly by the P. In DMA mode, the pin DACK/A4 is used as DACK, and A4 of the A-bus or AD-bus coming from the P must not be used as an address line for the DELIC. In this case A4 is driven internally to `0'. Note: In de-multiplexed mode AD4 should be connected to DELIC's D4input pin. Non-DMA mode This is the default mode (after reset).The general Mailbox and the DMA Mailbox data registers are concatenated into one double-sized general Mailbox, accessible by the P. This broad Mailbox consists of a dedicated P Mailbox and a DSP Mailbox. Each of them contains 32 data bytes and 1 command byte. In non-DMA mode, DACK/A4 is used as A4, in order to include the DMA Mailbox data registers in the P interface address space. 3.4.4 DELIC External Interrupts The DELIC contains only one source for an external interrupt - the general Mailbox. This interrupt source is the OCMD register of the DSP Mailbox. Releasing the interrupt is done by the P resetting bit OBUSY:BUSY. Masking it may be done by resetting the MASK bit of the P interface Configuration Register (MCFG:IMASK). The interrupt vector issued is the contents of the DSP Mailbox command register MCMD. In Motorola mode, the interrupt vector is issued upon the first IACK pulse, while in Infineon/Intel mode it is issued upon the second IACK pulse. In the latter case, the interrupt vector due to the first IACK pulse (if needed), should be issued by an external interrupt controller. Data Sheet 66 2003-07-31 PEB 20570 PEB 20571 Interface Description 3.5 JTAG Test Interface The DELIC provides fully IEEE Standard 1149.1 compatible boundary scan support to allow cost effective board testing. It consists of: * Complete boundary scan test * Test access port controller (TAP) * Five dedicated pins: JTCK, TMS, TDI, TDO (according to JTAG) and an additional TRST pin to enable asynchronous resets to the TAP controller * One 32-bit IDCODE register 3.5.1 Boundary Scan Test Depending on the pin functionality one or two boundary scan cells are provided. Pin Type Input Output Number of Boundary Scan Cells 1 2 Usage Input Output, enable When the TAP controller is in the appropriate mode data is shifted into/out of the boundary scan via the pins TDI/TDO using a clock of up to 6.25 MHz on pin JTCK. The sequence of the DELIC pins can be taken from the BSDL files. 3.5.2 TAP Controller The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE 1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change. The TAP controller supports a set of 5 standard instructions: Table 26 Code 0000 0001 0010 0011 1111 TAP Controller Instruction Codes Instruction EXTEST INTEST SAMPLE/PRELOAD IDCODE BYPASS Function External testing Internal testing Snap-shot testing Reading ID code register Bypass operation Data Sheet 67 2003-07-31 PEB 20570 PEB 20571 Interface Description EXTEST is used to verify the board interconnections. When the TAP controller is in the state "update DR", all output pins are updated with the falling edge of JTCK. When it has entered state "capture DR" the levels of all input pins are latched with the rising edge of JTCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD. INTEST supports internal chip testing. When the TAP controller is in the state "update DR", all inputs are updated internally with the falling edge of JTCK. When it has entered state "capture DR" the levels of all outputs are latched with the rising edge of JTCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD. Note: 0011 (IDCODE) is the default value of the instruction register. SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is used to either preload (TDI) or shift out (TDO) the boundary scan test vector. Both activities are transparent to the system functionality. IDCODE The 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to '1'. The code for the DELIC version 3.1 is '0100'. Version 0100 Device Code 0000 0000 0101 0111 Manufacturer Code 0000 1000 001 1 Output --> TDO Note: In the state "test logic reset" the code "0011" is loaded into the instruction code register. BYPASS, a bit entering TDI is shifted to TDO after one JTCK clock cycle, e.g. to skip testing of selected ICs on a printed circuit board. Data Sheet 68 2003-07-31 PEB 20570 PEB 20571 Functional Description 4 Functional Description As the functionality of the DELIC-PB comprises the functionality of the DELIC-LC, the following chapter describes the functionality of the DELIC-PB. The differences between the two chip versions (considering also the firmware) can be seen below: Table 27 Differences Between DELIC-LC and DELIC-PB DELIC-LC Cha. 0 2 MBit/s Cha. 0..23 not available not available; it is used to increment the general mailbox 256 no no no without threshold no DELIC-PB Cha. 0..3 8 MBit/s Cha. 0..31 available can be used for DMA operation or as general mailbox variable, limited by DSP-RAM yes yes yes with threshold yes Functionality GHDLC channels (maximum configuration) GHDLC maximum data rate HDLC channels (maximum configuration) DMA interface DMA- mailbox Number of switching connections (8-bit) Multi-bit switching (1-bit, 2-bit, 3-bit...7-bit) DECT-synchronization and delay measurement support 'Firmware Alive Indication' function DSP- Run time statistic counter DSP-PBX-library for conferencing, tone generation/ detection, DTMF receiver/ generator music on hold1) Free programmability of DSP-system 1) no yes These libraries are included in the DELIC-PB configurator. Data Sheet 69 2003-07-31 4.1 Figure 21 3.3 V 2x IOM /GCI 3 1 ... Data Sheet IOM Unit PCM Unit MUX PCM/ LNC2..3 2 x 2.048 Mbit/s or 1 x 4.096 Mbit/s Different Lines 5V t/r S/T Upn Uk0 PRI Layer-1 ICs 0 Block Diagram HDLC Unit 5 Subscribers 3.3 V GHDLC Unit LNC0 Upn 2 8 x UPN/ S/T 16 IOM-2000/ LNC16 MUX TRANSIU 16 DSP OAK+ Memory Different Lines: Upn or S/T Functional Overview and Block Diagram 70 REFCLK Clocks DSP 16.384 MHz S/T P Mail Box DMA Mail Box 4 VIP 0 Interrupt Controller JTAG 8 3 VIP 1 PLL 61.44 MHz VIP 2 VIP/ VIP-8 DMA Interface INT 5 TEST P Bus DELIC P Siemens C166 DMAC MEMORY PEB 20570 PEB 20571 Functional Description 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2 4.2.1 IOM-2000 Transceiver Unit (TRANSIU) IOM-2000 Features * The TRANSIU controls up to 24 layer-1 channels via up to three VIP/ VIP8 connected to IOM-2000 interface * IOM-2000 interface: all channels may be programmed in the IOM-2000 to: -UPN interface -S/T interface in LT-S (subscriber master) or LT-T (trunk slave) mode Note: The number of S/T interfaces in VIP PEB 20590 is limited to 4. Therefore it is required to program the IOM-2000 correctly to the required mode (refer to Table 49) * Clock rates: 3.072 Mbit/s (1 VIP), 6.144 Mbit/s (2 VIPs) or 12.288 Mbit/s (3 VIPs) * Data and maintenance bit handling for S/T and UPN interface, including multiframe control and D-channel collision control. Scrambling / Descrambling (in DELIC) The B-channel data on the Up interface is scrambled in order to ensure that the receiver at the subscriber terminal gets enough pulses for a reliable clock extraction (flat continuous power density spectrum is provided), and to avoid periodic patterns on the line. A descrambler is implemented in the opposite direction to extract the received Up data. The scrambling is done according to ITU V.27, OCTAT-P and DASL. 4.2.2 IOM-2000 Initialization Channel Programming Each IOM-2000 channel may be configured in the TRANSIU as: * UPN mode * S/T channel in LT-S mode * S/T channel in LT-T mode Data Rate Programming The IOM-2000 supports three configurations regarding the number of VIPs connected via IOM-2000: * One VIP connected at data rate of 3.072 Mbit/s: 8 IOM-2000 channels at a clock rate of 3.072 MHz (for LT-T mode please refer to Page 62) * Two VIPs connected at data rate of 6.144 Mbit/s: 16 IOM-2000 channels at a clock rate of 6.144 MHz Data Sheet 71 2003-07-31 PEB 20570 PEB 20571 Functional Description * Three VIPs connected at data rate of 9.216 Mbit/s: 24 IOM-2000 channels at a clock rate of 12.288 MHz. (Note the difference between clock rate and actual data rate) 4.2.3 Initialization of the VIP During startup the VIP requires 3 frames with the right FSC and DCL_2000 to synchronize to the DELIC. During this time the VIP is not able to detect commands or data from the DELIC. Therefore, the delayed reset signal RESIND of the DELIC should be used to reset the VIP. 4.2.4 IOM-2000 Command and Status Interface All Command/Status bits used for VIP channel programming are divided into one group used only during initialization, and one group used during normal operation. 4.2.4.1 Initialization Mode Command Bits The bits of this group are used for VIP initialization or in operation modes where an immediate reaction is not required. The initialization group includes command bits and the channel address, stored in register TICCMR. Note: The usage of this group of bits is limited in a way that only one channel may be accessed in each frame. In test mode, the command word to VIP_n (CMD_n) and to Channel_m of VIP_n (CMD_n_m) may be read by the DELIC in the next frame after issuing bits 'RD_n' or 'RD'. The VIP mirrors the command word exactly as it was received, despite the bits 'WR', 'WR_ST', 'RD'. The VIP status is saved in the TRANSIU initialization status (TICSTR) register, which includes status bits and the channel address. Note: The commands must not be read during normal operation, since in this case the reporting of the VIP status to the DELIC would not be possible. 4.2.4.2 Operational Mode Command/Status Bits The bits of this group are used during normal operation, hence they are evaluated in every frame. They include all VIP receiver status bits and some of the command bits. The operational mode command/status bits are buffered in the Data RAM. The VIP receiver status bits do not reflect a status change, but the status itself, i.e. the current value of the line interface INFOs, until the values change. The FECV is only reported to the DELIC upon changes. 4.2.4.3 Command/Status Transmission The command/status bits are transmitted/received by the TRANSIU at the same rate as data transmission rate, starting with the 8 kHz FSC. Data Sheet 72 2003-07-31 PEB 20570 PEB 20571 Functional Description Transmit Direction * The command information per VIP is prepared by the DSP in the VIPCMR0-2 registers * The command bits from initialization command group are prepared by the DSP in the TICCMR register for one of the channels * TRANSIU operation mode command format in the Data RAM Receive Direction * The received status per VIP is stored in the VIPSTR0-2 registers * If the "read_status" command was transmitted in the previous frame for one of the channels, the received status from this channel is saved in the TICSTR register together with the 5-bit channel address * TRANSIU operation mode status format in the Data RAM Data Sheet 73 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2.4.4 Command and Status format in the Data RAM The operational mode command and status bits usually are served completely by the firmware. So there is no need to set this bits by the user. Operational Mode Command bits in the data RAM: Address:see memory map 7 6 5 4 3 data byte 1 data byte 2 data byte 3 x x x SMINI(2:0) MSYNC WR_ST 2 1 0 WR_ST Write Command to TST1 Bits (S/T, UPN) 0 = Data sent in these bits is invalid 1 = SMINI(2:0) and MSYNC contain valid data Multiframe Synchronization (LT-T) 0 = VIP mirrors the FA-bit 1 = VIP stops the FA-bit mirroring (for multiframe synchronization) State Machine Initialization (S/T, UPN) Command to VIP from the DELIC layer-1 state machine. Depending on the state, the VIP may transmit data on the UPN or S/T interface. The VIP responds by sending the receiver status bits STAT_n_m.RxSTA(1:0) to the DELIC. 000 = INFO 0 in S/T or UPN 001 = INFO 1w in UPN 010 = INFO 1 in LT-T, INFO 2 in LT-S or UPN 011 = INFO 3 in LT-T, INFO 4 in LT-S or UPN 100 = Test mode 'Send Continuous Pulses SCP': '1s' transmitted at 96 kHz (UPN) and at 192 kHz S/T) 101 = Test mode 'Send Single Pulses SSP' (at 2 kHz burst rate) all other states are reserved MSYNC SMINI(2:0) Data Sheet 74 2003-07-31 PEB 20570 PEB 20571 Functional Description Operational Mode Status bits in the data RAM: Address:see memory map 7 6 5 4 data byte 1 data byte 2 data byte 3 x MSYNC FCV FSYNC SLIP FECV RxSTA(1:0) 3 2 1 0 RxSTA(1:0) Receiver Status Change (S/T, UPN) 00 = Receiver is not synchronized to the line; no signal on line (INFO 0) 01 = Level detected on line (any signal) (INF 1 in LT-S mode) 10 = Receiver is synchronized to the line, but not activated (INFO 2 in LT-T mode) 11 = Receiver is synchronized and activated (INFO 4 for LT-T mode INFO 3 for LT-S and UPN) Far-end Code Violation (S/T, UPN) 0 = Normal operation 1 = Illegal code: FECV according to ANSI T1.605 detected (S/T) Frame Slip Detected (LT-T) 0 = No frame slip detected 1 = A frame slip of more than 20 s was detected on the LT-T channel F-Bit Synchronous (S/T + UPN test mode only!) Code Violation in F-Bit detected (UPN test mode only!) Multiframe Synchronous (UPN), Level Detected (S/T), test mode! FECV SLIP FSYNC * FCV * MSYNC / LD * Note: with * marked bits are not evaluated by the DELIC, only for VIP testing. Bits SLIP, FECV and are directly available to the DSP software in the TRANSIU receive data RAM. Data Sheet 75 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2.5 UPN Mode Frame Structure The UPN interface uses a ping-pong technique for 2B+D data transmission over the line. UPN is always point-to-point. The frame structure of the data transfer between the exchange (PBX, LT) and the terminal (TE) is depicted in Figure 22. * The PBX starts a transmission every 250 s (burst repetition period). * A frame transmitted by the exchange (PBX) is received by the terminal (TE) after a given propagation delay td. * The terminal waits a minimum guard time (tg = 5.2 s) while the line clears. Then a frame is transmitted from the terminal to the PBX. * The time between the end of reception of a frame from the TE and the beginning of transmission of the next frame by the LT must be greater than the minimum guard time. The guard time in TE is always defined with respect to the M-bit. Data Sheet 76 2003-07-31 PEB 20570 PEB 20571 Functional Description tr LT TE/PT td tg td LF 1 B1 8 B2 8 D 4 99 s LF-Framing Bit B1 8 B2 8 M1) DC 2) 1 #Bits 1) M Channel Superframe CV T S T CV T S T CV ITD00823 CV = Code Violation: for Superframe synchronization T = Transparent Channel (2 kbit/s) S = Service Channel (1 kbit/s) 2) DC balancing bit, only sent after a code violation in the M-bit position and in special configurations. Timings: t r = burst repetition period = 250 s t d = ine delay = 20.8 s maximum t g = guard time = 5.2 s minimum Figure 22 UPN Interface Frame Structure Up Coding (in VIP) The coding technique used on the Up interface is a half-bauded AMI code (with a 50 % pulse width (refer to Figure 23). A logical `0' corresponds to a neutral level, logical `1's are coded as alternate positive and negative pulses. Code violation (CV) is caused by two successive pulses with the same polarity. The AMI coding includes always the data bits going on the Up interface in one direction. Consequently there is a separate AMI coding unit for data from the DELIC to the VIP implemented in the VIP, and vice versa. Data Sheet 77 2003-07-31 PEB 20570 PEB 20571 Functional Description Figure 23 AMI Coding on the Up Interface Data Sheet 78 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2.6 UPN Interface The data is received and transmitted at a nominal bit rate of 384 kbit/s. In the first half of the 4 KHz frame data is transmitted and `zeros' are received, in the second half of the frame `zeros' are transmitted and data is received (Ping-pong interface). Tx: VIP hardware: DC-bit generation IOM-2000 hardware: LF-bit generation B-channel scrambling 250 s TRANSIU DSP DSP software: Generation of complete Up frame M-bit handling DELIC VIP Tx DC Rx FIFO Tx buffer Rx buffer State Machine SYNC F CV Rx Rx: VIP hardware: FIFOs: - for jitter compensation TRANSIU hardware: LF-bit recognition DC-bit discard B-channel descrambling DSP software: M-bit handling Figure 24 Handling of UPN Frame (one Channel) Transmit Direction * Since the DELIC is always master on the Up-interface, all transmitted Up frames always start with the FSC-2000 (the transmission starts from ch-0.bit-0 which is followed by ch_1.bit_0, ch_2.bit_0,... ch_7.bit_0, ch_1.bit_1, etc.; see also Figure 12) * The LF-bit is generated and inserted at the beginning of the frame. * B-channel data prepared by the DSP is scrambled and inserted into the U-frame. * D- channel data and M-bit, prepared by the DSP, are inserted into the transmitted Up frame by the TRANSIU. Receive Direction * The received frame start is recognized by the LF-bit, which is always logical `1' (this is the first `1' received after the FSC_2000). Since the received frames start at different points of time (due to the different line delays) the frame start recognition is performed for each channel separately * The B-channel data is descrambled * The B- and D-channel data and M-bit are stored in the Data RAM Data Sheet 79 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2.7 4.2.7.1 UPN Framing Bit Description Framing Bit (LF-Bit) On the UPN interface the framing (LF) bit is always logical `1'. In the transmit direction the LF-bit is inserted by the TRANSIU at the beginning of every transmitted UPN frame. The VIP assumes the start of the UPN frame when detecting the first '1' (LF-bit) in the data stream on IOM-2000 DX line together with the 8 kHz IOM-2000 FSC pulse. This is required due to the 8 kHz clock rate of the FSC signal in comparison to the 4 kHz frame length in the UPN interface. The code violation in the LF position is generated by the VIP when INFO1 is transmitted, according to the DSP command bits SMINI(2:0). In the receive direction the first `1' recognized on the line after "no signal", which is represented by logical `0', is treated as the LF-bit. The code violation in the LF-bit position is recognized by the VIP when INFO 2 is received. This information is forwarded to the DELIC as part of the VIP receiver status bits RxSTA(1:0). 4.2.7.2 Multiframing Bit (M-Bit) On the UPN interface multiframes are composed of four UPN frames. The multiframe is included at the M-bit position. Every fourth M-bit, a code violation indicates the start of a new multiframe. In transmit direction, the VIP extracts the multiframe bits out of the IOM-2000 data coming from DELIC and inserts them in the UPN frame at the line side. In receive direction, the VIP extracts the multiframe bits out of the data coming from the UPN line and inserts them in the IOM-2000 frame to the DELIC. A multiframe counter in the VIP guarantees the timing of the multiframe. It is synchronized (reset) every 20th UPN frame (=every 40th IOM-2000 frame) by the command bit 'SH_FSC' issued by the DELIC. Note: The SH_FSC bit performs the functionality of the short FSC pulse in OCTAT-P and QUAT-S. T-bit The T-bit received on the UPN line is inserted by the VIP in the IOM-2000 data receive (DR) line at the multiframe (M-bit) position in every frame; i.e. not only at the usual T-bit position every third frame, but also at the S-bit position and the code violation (CV) position.In transmit direction, the T-bit value is sent in the data stream from the DELIC to the VIP, and passed on transparently to the UPN terminal. The T-bit value may be programmed in DELIC's data RAM. It is required e.g. for DECT synchronization. Data Sheet 80 2003-07-31 PEB 20570 PEB 20571 Functional Description S-bit The S-bit received on the UPN line interface is extracted by the VIP out of the data stream, and is logical OR' ed with the detected far-end code violation. The result is sent to the DELIC as status bit 'FECV'. In transmit direction, the S-bit value is sent in the data stream from the DELIC to the VIP, and passed on transparently to the UPN terminal. The S-bit value may be programmed in DELIC's data RAM. It is required e.g. for switching a digital loop in the terminal. CV-bit The code violation bit received on the line is not transmitted to the DELIC. 4.2.7.3 DC-Balancing Bit A DC-balancing bit is inserted by the VIP according to the Balancing Bit Control (BBC) bit transmitted to the VIP on the command line. In receive direction, the DC balancing bit is received, but not evaluated. 4.2.7.4 UPN Mode Data Format The data is received and transmitted at a nominal bit rate of 384 kbit/s. In the first half of the 4 kHz UPN frame data is transmitted and `zeros' are received, in the second half of the frame `zeros' are transmitted and data is received. Scrambling and de-scrambling of the B-channel data is done automatically. The received and transmitted data is stored in the Data RAM in the following format: UPN Mode Receive / Transmit Data Format 7 6 5 4 3 2 1 0 B1-channel data B2-channel data D-channel M-bit x x x x x Operation Mode Command/Status bits In transmit direction, depending on the multiframe position, the M-bit contains either the T-bit or the S-bit with the following functionality: * T-bit: a) D-channel available info to the terminal b) DECT synchronization signal * S-bit: switches remote loop in terminal device Data Sheet 81 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2.7.5 UPN Scrambler/Descrambler B-channel data on all UPN channels of the IOM-2000 interface is scrambled to give a flat continuous power density spectrum on the line. Scrambling is done according to ITU-T V.27 with the generator polynomial 1 + x6 + x7, OCTAT-P and DASL. Initialization via History RAM (HRAM) The scrambler is activated/deactivated for each UPN channel separately by a DSP write to the history RAM address. During initialization the DSP writes a value with '0' in its LSB (other bits are of no importance) to every History RAM address associated to an UPN channel that is not to be scrambled, and a value with '1' in its LSB for every UPN channel that must be scrambled. The same values must be written to the descrambler history RAM. The HRAM addresses are: * 0x9000 - 0x9017 (scrambler UPN channel 0..23) * 0x9020 - 0x9037 (descrambler UPN channel 0..23) For example, in order to activate scrambling and descrambling for channel number 3, the DSP must execute two write operations as follows: * Write "xxxxxxxxxxxxxxx1" to address 0x9002 * Write "xxxxxxxxxxxxxxx1" to address 0x9022 These writes are executed only when the scrambler is in idle mode, i.e. value 0x0003 was written by the OAK to address 0xD010. Note: The HRAM setting is handled by the DSP according to the scrambler mode register (address 0xD010). 4.2.8 DECT Synchronization for UPN- Interface For DECT systems the DELIC supports synchronization of the different radio base stations (RBS). Synchronization is controlled by the DSP via the T-bit in the UPN-frame. Data Sheet 82 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2.9 S/T Interface Frame Structure The S/T interface establishes a direct link between the VIP and connected subscriber terminals or to the Central Office. It consists of two pairs of copper wires: one for the transmit and one for the receive direction. Direct access to the VIP's S/T interface by the DELIC is not possible. 2B+D user data as well as S/Q channel information can be inserted and extracted via the IOM-2000 interface. Framing bits are generated and transmitted to the VIP by the DELIC. Transmission over the S/T interface is performed at a rate of 192 kbit/s. Pseudo-ternary coding with 100 % pulse width is used. 144 kbit/s are used for user data (36 bits of B1+B2+D) and 48 kbit/s (12 bits) are used for framing, S/Q and maintenance information. For each S/T channel, the VIP uses two symmetrical, differential outputs (SX1, SX2) and two symmetrical, differential inputs (SR1, SR2). These signals are coupled via external circuitry and two transformers onto the 4 wire S/T interface. The nominal pulse amplitude on the S/T interface is 750 mV (zero-peak). S/T Coding The following figure illustrates the code used. A binary ONE is represented by no line signal (0 V). Binary ZEROs are coded with alternating positive and negative pulses with two exceptions: the first binary ZERO following the framing balance bit is of the same polarity as the framing-balancing bit, and the F-bit is always at positive level (required code violations). Figure 25 S/T Interface Line Code (without code violation) A standard S/T frame consists of 48 bits. In the direction TE NT the frame is transmitted with a 2-bit offset. For details on the framing rules please refer to ITU I.430. The following figure illustrates the standard frame structure for both directions (NT TE and TE NT) with all framing and maintenance bits. Data Sheet 83 2003-07-31 PEB 20570 PEB 20571 Functional Description Figure 26 Frame Structure at Reference Points S and T (ITU I.430) -F - L. -D -E - FA -N - B1 - B2 -A -S -M Framing Bit D.C. Balancing Bit D-Channel Data Bit D-Channel Echo Bit Auxiliary Framing Bit B1-Channel Data Bit B2-Channel Data Bit Activation Bit S-Channel Data Bit Multiframing Bit F = (0b) code violation, identifies a new frame (always positive pulse) L. = (0b) number of binary ZEROs sent after the last L. bit was odd signaling data specified by user E = D if D-channel is not blocked, otherwise E = D. (ZEROs always overwrite ONEs See section 6.3 in ITU I.430 N = FA User data User data A = (0b) INFO 2 transmitted A = (1b) INFO 4 transmitted S1 or S2 channel data M = (1b) Start of new multi-frame In LT-T configurations, the DELIC receives the reference clock from the Central Office via the IOM-2000 REFCLK line. The VIP selects the reference clock source via two multiplexers. The source may be either one of the 8 VIP channels operated in LT-T mode or the CLKIN pin when driving multiple cascaded VIPs on the IOM-2000. Data Sheet 84 2003-07-31 PEB 20570 PEB 20571 Functional Description Ch_0 VIP_0 REFCLK_0 1.536 MHz XCLK DR DELIC CH_7 CLKIN_0 Ch_0 Reference Clock LT-T Ch_7 VIP_1 REFCLK_1 VIP_n REFSEL CLKIN_1 Ch_0 EXREF REFCLK Ch_0 VIP_2 REFCLK_2 Ch_7 Ch_7 CLKIN_2 CLKIN Figure 27 Reference Clock Selection for Cascaded VIPs on IOM-2000 Note: A change in the reference clock source must not result in a FSC jump greater than the difference of the clock phase before and after the change, which otherwise would result in big frame slips. Data Sheet 85 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2.9.1 Tx: LT-S mode VIP hardware: F-bit & CV generation Inversion of data (B1, B2, D) E-bit mirroring TRANSIU hardware: F-, L-, N-bit generation DSP software: Generation of complete S frame Multiframe generation S-bit handling (8-bit service ch.) Control of E-bit mirroring 250 s TRANSIU Tx DELIC DSP S-FIFO VIP F F,L INV INV SYNC M Tx buffer Rx buffer FA Rx Rx FIFOs Q-FIFO Rx: VIP hardware: F-bit & CV detection FIFOs: -for jitter etc. Inversion of data (B1, B2, D) TRANSIU hardware: F-bit recognition L-bit discard Control of E-bit mirroring DSP software: FA-bit handling (4-bit Q-channel) INFO 2,4 recognition Figure 28 Handling of So Frame in LT-S Mode (One Channel) Transmit Direction * Since the DELIC is master in the LT-S mode, all transmitted frames always start with the FSC-2000 (the transmission starts from ch-0.bit-0 which is followed by ch_1.bit_0, ch_2.bit_0,... ch_7.bit_0, ch_0.bit_1, etc.; see also Figure 12) * The F-, L- and N-bits are generated and inserted into the S/T frame * The information about D-channel availability is transmitted at the E-bit position * The B- and D-channel data, A-, Fa-, M- and S-bits are prepared by the DSP and inserted into transmitted S/T frame by the IOM-2000 Receive Direction * The received frame start is recognized by the F-bit. Since the received frames start at different points of time (due to the different line delays) the frame start recognition is performed for each channel separately * The received L-bits are discarded * The B- and D-channel data bits and Fa-bit are arranged in the Data RAM Data Sheet 86 2003-07-31 PEB 20570 PEB 20571 Functional Description D-echo Bit Generation in LT-S Mode In the LT-S mode, the last received D-bit has to be reflected in the next available E-bit (E=D). If there are no HDLC controllers available, the D-channel is blocked (E=D is transmitted). Since it is necessary to meet the ITU requirement to react immediately (i.e., even when line delays of several bits have occurred) upon the reception of a D-bit by issuing the E-bit, the E-bit has to be inserted by the VIP. The information about the Dchannel availability is provided to the VIP in the E-bit data field. Table 28 bit0 (data) 0 1 D-Echo Bit bit1(control) 0 0 The transmitted E-bit is equal to the received D-bit The transmitted E-bit is equal to the inverted received D-bit Information about the availability of HDLC controllers is provided to the IOM-2000 by the DSP. VIP E D DELIC DX E E/D logic DR D DSP Figure 29 D-Echo Bit Generation Data Sheet 87 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2.9.2 Tx: LT-T Mode VIP hardware: F-bit & CV generation Inversion of data (B1, B2, D) TRANSIU hardware: F-, L-bit generation DSP software: Generation of complete S frame Q-channel handling D-channel priority handling 250 s TRANSIU Tx DSP Q-FIFO DELIC VIP D INV Tx buffer Rx buffer SYNC FA E/D Rx FIFOs Rx INV E F,L S-FIFO Rx: VIP hardware: F-bit & CV detection E-bit collision detection FIFOs: - for jitter etc. Inversion of data (B1, B2, D) TRANSIU hardware: N- and L-bit discard E-/D-bit handling, collision detection DSP software: FA-bit check every 5th frame M-bit & S-channel handling A-bit handling (INFO 2 or 4) Figure 30 Handling of So Frame in LT-T Mode (One Channel) Receive Direction * The received frame start is recognized by the F-bit. Since the DELIC is a slave in the LT-T mode, the received frames may start at any point of time, and the frame start recognition is performed for each channel independently. * The received L- and N-bits are discarded * The received E-bit is compared with the last transmitted D-bit--if collision is detected on the D-channel it is reported to the DSP * The received B- and D-channel data bits, A-, Fa-, M- and S-bits as well as the information about collision detected on the D-channel are stored in the Data RAM. Transmit Direction * According to ITU.430, the 2-bit delay between received and transmitted frames must be guaranteed at the TE (i.e., this delay must be controlled by the VIP). Because of the VIP delay in both receive and transmit directions (this delay is the same for all LTT lines and is always constant (TBD during VIP design)), the TRANSIU starts the LTT frame transmission before the F-bit of received frame is recognized. * The F- and L-bits are generated and inserted into the S/T frame Data Sheet 88 2003-07-31 PEB 20570 PEB 20571 Functional Description * The B-channel data is prepared by the DSP in the Data RAM and inserted into the downstream frame by the TRANSIU * If collision was detected on the D-channel, the data transmission on this channel is blocked by the TRANSIU and the 1's are sent on the D-channel instead of the data from the Data RAM until the data sending is enabled by the DSP * The B- and D-channel data bits and Fa-bit are prepared by the DSP in the Data RAM in the same format as LT-S received frames Collision Detection on D-channel in LT-T Mode The collision is detected on the D-channel when the received E-bit is not equal to the last transmitted D-bit. * The TRANSIU compares the E-bit with the D-bit * When the collision is detected, the TRANSIU indicates collision to the DSP, and starts to send 1's on the D-channel. * The priority mechanism is implemented in software. The TRANSIU provides the following information to the DSP (2 bits per LT-T - configured channel, which are stored in the Data RAM, see "LT-T Mode Receive Data Format" on Page 94. -Collision detection on D-channel (Cl-bit): `0' - no collision in the D-channel, `1' - collision was detected in the D-channel. -Collision detection bit number: `0' - collision was detected in the 1-st bit of the frame, `1' - collision was detected in the 2-nd bit of the frame. * The DSP counts to 8/9 (higher priority) or 10/11 (lower priority) and enables the TRANSIU to transmit the data on the D-channel at the end of counting. The TRANSIU stops D-channel blocking immediately, all relevant data (end of Idle or start of the flag) is already prepared by the DSP in the Data RAM. * If the new collision was detected by the TRANSIU during the current collision, the DSP resets the priority mechanism counters and starts counting from the beginning. Data Sheet 89 2003-07-31 PEB 20570 PEB 20571 Functional Description TRANSIU D Data buffer E E/D logic Collision Status HDLCU DSP DELIC Figure 31 Collision Detection in the LT-T Mode 4.2.10 S/T Mode Control and Framing Bits on IOM-2000 4.2.10.1 Framing Bit (F-Bit) The framing (F) bit is recognized on the TRANSIU interface, when both data and control bits are equal to `1'. In the transmit direction the data and control bits are inserted by the TRANSIU at the beginning of every transmitted frame; in the receive direction the framing bit is used for frame start recognition. 4.2.10.2 Multiframing Bits In S/T interface, the multiframe includes 20 S/T frames. The start of a multiframe is indicated by the M- and Fa-bits (the M-bit is set to `1' in every 20th frame, the Fa-bit is set to `1' in every 5th frame). The S/Q channel provides the additional capability for data exchange between LT-S and TE or between the Central Office (CO) and the LT-T at the multiframe level. In the LT-Sto-TE direction the S-channel (S-bit in S/T frame) is used. In the opposite direction (TE to LT-S) the data is transferred on the Q-channel. The Q-bits are defined to be the bits in the Fa bit position of every 5th frame. The Q-bit position is identified by Fa = `1' in the TE to LT-S direction. A multiframe is provided for structuring the Q-bits in groups of four (Q1-Q4). The Q- and S-channel coding with respect to the frame number is shown in Table 29. Data Sheet 90 2003-07-31 PEB 20570 PEB 20571 Functional Description S TE Q LT-S VIP LT-T IOM-2000 DELIC S CO Q Figure 32 S/Q Channel Assignment Data Sheet 91 2003-07-31 PEB 20570 PEB 20571 Functional Description Table 29 S/T Mode Multiframe Bit Positions LT-S to TE or LT-S to TE or CO to LT-T, CO to LT-T, Fa bit position M-bit 1 0 1 0 1 0 1 0 ... 1 0 0 0 0 0 0 0 ... LT-S to TE or CO to LT-T, S-bit S11 S21 S12 S22 S13 S23 S14 S24 ... TE to LT-S or LT-T to CO Fa bit position Q1 0 Q2 0 Q3 0 Q4 0 ... Frame number 1 2 6 7 11 12 16 17 ... Note: 1.Only frame positions (within the 20-frame multiframe) that carry S- or Q-channel information are shown here 2.The Q- and S-bits, which are not used, are set to `1'. On the IOM-2000 interface, the S/T multiframe information is included in the DX/DR data stream (transparent to the VIP). The values of the multiframe are controlled by the DSP software in the DELIC. When multiframe synchronization is not achieved or lost, the VIP mirrors the received Fa bits. Once the multiframe synchronization is established, the DSP sends the multiframe synchronization command to the VIP (MSYNC bit). Upon reception of the MSYNC, the VIP stops mirroring the Fa -bit. 4.2.10.3 Fa/N Bit In the transmit direction the Fa/N bit pair is coded in such a way that N is the binary opposite of the Fa. The Fa bit is equal to binary `0', except every 5th frame when it is set to `1', which indicates the Q-bit position to the TE. The receive direction, the Fa bit positions represent the Q-channel. Data Sheet 92 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.2.10.4 DC-Balancing Bit (L-Bit) In transmit (downstream) direction the L-bit is generated in compliance with ITU-T I.430: * A balance bit is `0' if the number of 0's following the previous balance bit is odd. * A balance bit is `1' if the number of 0's following the previous balance bit is even. It is inserted by the VIP according to the Balancing Bit Control (BBC) bit sent to the VIP by the DELIC via the CMD line. In receive (upstream) direction, the DC balancing bit is received on the line, but not evaluated. 4.2.11 IOM-2000 Data Interface Data processing and frame handling in the TRANSIU is fully DSP controlled. Serial data received and transmitted on the TRANSIU Interface is arranged in the Shift Receive RAM and Shift Transmit RAM. The DSP processed bytes are stored in the TRANSIU Current Buffer. Every 8 kHz frame the TRANSIU and DSP Current Buffers are switched. 4.2.11.1 S/T Mode Data Format Data is received/transmitted at a nominal rate of 192 kbit/s. Each S/T data bit is translated into two bits on IOM-2000: data (bit0) and control (bit1). LT-S Mode Transmit Data Format 7 6 5 4 3 2 1 0 B1-channel data B2-channel data D-channel x Fa M S x x Operation Mode Command/Status bits LT-S Mode Receive Data Format 7 6 5 4 3 2 1 0 B1 - channel data B2 - channel data D-channel Fa x x x x x Operation Mode Command/Status bits Data Sheet 93 2003-07-31 PEB 20570 PEB 20571 Functional Description LT-T Mode Transmit Data Format 7 6 5 4 3 2 1 0 B1-channel data B2-channel data D-channel Fa x x x x x Operation Mode Command/Status bits LT-T Mode Receive Data Format 7 6 5 4 3 2 1 0 B1-channel data B2-channel data D-channel x Fa M S CBN CDI Operation Mode Command/Status bits CBN Collision Detection Bit Number 0 = Collision was detected in the first D-bit of the S-frame half (corresponds to the second echo-bit of the frame half) 1 = Collision was detected in the second D-bit of the S-frame half (corresponds to the first echo-bit of the frame half) Collision Detection Indication 0 = No collision in D-channel 1 = Collision in D-channel detected CDI 4.2.12 Test Loop The DELIC/VIP allows to set up internal as well as remote loops for testing by programming registers TICCMR and TUTRL. Note: Please refer also to the Application Note 'Test Loops in the VIP'. Data Sheet 94 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.3 4.3.1 IOM-2 Unit IOMU Features The IOMU provides the DSP access to incoming time slots from the IOM-2 interface. Features * DSP access for switching of B1 and B2 data to the PCMU, TRANSIU and IOMU (providing a constant switching delay of two 8 kHz frames) * DSP access for extracting D-channel information * DSP access for control of IOM-2 Command/Indication (C/I) and Monitor channel information Interface Configuration * Two IOM-2 ports providing up to 16 IOM-2 channels (up to 16 ISDN or 32 analog subscribers) * Available data rate modes: -One port of 384 kbit/s each (1 x 6 time slots per frame) -One port of 768 kbit/s each (1 x 12 time slots per frame) -Two ports of 2.048 Mbit/s each (2 x 32 time slots per frame) -One port of 4.096 Mbit/s (1 x 64 time slots per frame) * Single or double data rate clock selectable for data rates up to data rates up to 2.048 M bit/s * Programmable tri-state control for each port and channel (=4 time slots) * Push-pull or open-drain configuration * DRDY signal for D-channel control when connected to QUAT-S PEB 2084 Data Sheet 95 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.3.2 IOMU Functional and Operational Description IOM-2 Interface FSC DCL DD0 B1 B2 M D,C/I D.C/I M B2 B1 DELIC CLOCKS PCMU SWITCHING PCM Interface DU0 DD1 B1 B2 M D,C/I D.C/I M B2 B1 IOMU DU1 SWITCHING DRDY HDLCU IOM-2000 Interface IOM-2000 DSP Figure 33 IOMU Integration in DELIC 4.3.2.1 Frame-Wise Buffer Swapping The main task of the IOMU is the serial-to-parallel conversion of incoming IOM-2 data to a parallel data format which is directly read by the DSP. This access is required for the DSP to perform switching of B-channels, extraction of D-channels, and layer-1 control via the IOM-2 C/I and Monitor channels. The data conversion in the IOMU is done by frame-wise swapping based on a circular buffer structure. During each 8 kHz frame, one buffer is assigned to the IOMU (I-buffer), and the other one to the DSP (D-buffer). At the end of every frame, the buffers are swapped. 4.3.2.2 DSP Inaccessible Buffer (I-buffer) Logical Structure The logical partitioning of each frame buffer into input and output blocks is determined according to the requested data rate as shown in the table below. Data Sheet 96 2003-07-31 PEB 20570 PEB 20571 Functional Description Table 30 Data Rate in0 2 x 2.048 Mbit/s 1 x 384 kbit/s 1 x 768 kbit/s 1 x 4.096 Mbit/s 00H - 1FH 00H - 05H 00H - 0BH 00H - 3FH I-Buffer Logical Memory Mapping Input Blocks in1 20H - 3FH ---Output Blocks out0 40H - 5FH 40H - 05H 40H - 4BH 40H - 7FH out1 60H - 7FH ---- 4.3.2.3 DSP Access to the D-Buffer The D-buffer is mapped to a fixed DSP address space. Every DSP access to the D-buffer space is directed automatically to the appropriate sub-buffer. E.g. the address of time slot 5 is 0x8005 in receive and 0x8045 in transmit direction. . Table 31 Data-Rate Mode D-Buffer Address Space D-Buffer in0 8000H 801FH 8000H 8005H 8000H 800BH 8000H 803FH in1 8020H 803FH out0 8040H 805FH 8040H 8045H 8040H 804BH 8040H 807FH out1 8060H 807FH - 2 x 32 time slots/frame 1x6 time slots/frame 1 x 12 time slots/frame 1 x 64 time slots/frame Data Sheet 97 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.3.2.4 Circular Buffer Architecture DELIC IOMU DU1 DU0 Serial Parallel Parallel DD1 DD0 Serial Frame-wise Buffer Swapping every frame I-BUFFER in0 in1 out0 out1 Belongs to the IOMU D-BUFFER in0 in1 out0 out1 Belongs to the DSP DSP Figure 34 IOMU Frame-Wise Circular-Buffer Architecture The following description analyses the frame-wise circular-buffering scheme, on a frame to frame basis. Assume that during frame n, buffer-0 is used as I-buffer, while buffer-1 is used as Dbuffer. The IOMU stores the incoming frame-n time-slots in buffer-0 input-blocks and drives outward the frame n time-slots which are read from buffer-0 output-blocks. At the same time the DSP reads the time-slots that arrived during frame n-1 (the previous frame) from buffer-1 input-blocks and prepares the time-slots to be driven outward in the next frame, frame n+1, in buffer-1 output blocks. Data Sheet 98 2003-07-31 PEB 20570 PEB 20571 Functional Description A buffer-swapping takes place at the end of frame-n, as at the end of any other frame. This means that during frame-n+1, buffer-1 is used as I-buffer, while buffer-0 is used as D-buffer. During this frame the IOMU handles the incoming and outgoing frames n+1, and writes/reads the time-slots to/from buffer-1 input/output blocks. In parallel, the DSP handles buffer-0 input and output blocks. It reads the frame-n up-stream time-slots from the input-blocks and prepares the frame-n+2 down-stream time-slots in the output blocks. The buffer-swapping at the end of frame-n+1 re-assigns buffer-0 as the I-buffer and buffer-1 as the D-buffer (exactly as in frame-n). Figure 35 illustrates the frame-wise circular-buffering scheme during two consecutive frames, as described in the previous example. FRAME n BUFFER 0 frame n written by the IOMU, from DU FRAME n+1 BUFFER 0 frame n read by the DSP in0 in1 out0 out1 Used as I-buffer in0 in1 out0 out1 Used as D-buffer SWAP BUFFER 1 frame n read by the IOMU, to DD frame n+2 written by the DSP BUFFER 1 frame n-1 read by the DSP in0 in1 out0 out1 Used as D-buffer frame n+1 written by the IOMU, from DU in0 in1 out0 out1 Used as I-buffer frame n+1 written by the DSP frame n+1 read by the IOMU, to DD Figure 35 The Circular-Buffer During two Consecutive Frames Data Sheet 99 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.3.2.5 * * * * IOM-2 Interface Data Rate Modes The IOMU may support different serial data rates of the IOM-2 interface: 384 kbit/s (6 time slots per frame) 768 kbit/s (12 time slots per frame) 2.048 Mbit/s (32 time slots per frame = 8 IOM-2 channels per frame) 4.096 Mbit/s (64 time slots per frame = 16 IOM-2 channels per frame) The IOMU circular buffer may handle up to 64 time slots per frame. Thus, when in 4.096 Mbit/s mode, only IOM-2 port 0 is used. In this case IOM-2 port 1 remains in IDLE mode, i.e. the DD1 output pin is tri-stated. Table 32 DCL Frequency in Different IOM-2 Modes IOM-2 Mode 1x384 kbit/s 384 kHz 768 kHz 1x768 kbit/s 768 kHz 1536 kHz 2x2.048 Mbit/s 1x4.096 Mbit/s 2.048 MHz 4.096 MHz 4.096 MHz - Single/Double Rate DCL Mode Single Double The IOMU meets the IOM-2 interface timing specifications as described below. Single Data Rate DCL Mode * Serial transmission via DD0/DD1 with every DCL rising edge * Sampling of the incoming serial data (DU0/DU1) with every DCL falling edge * Sampling FSC with every DCL falling edge. Sampling of FSC = 1 after sampling of FSC = 0 is considered to be the start of a frame. Double Data Rate DCL Mode * * * * Two DCL cycles per bit (the bits are aligned to the frame start) Serial transmission via DU0/1 with every second DCL rising edge. Sampling of incoming serial data (DD0/1) with the second DCL falling edge of each bit. Sampling of FSC every DCL falling edge. Sampling of FSC = 1 after sampling of FSC = 0, is considered to be the start of a new frame. Figure 36 shows the IOM-2 interface timing with single and double rate DCL. Data Sheet 100 2003-07-31 PEB 20570 PEB 20571 Functional Description FSC Single Data Rate DCL Frame Start DCL DD0/1 DU0/1 TS31 bit0 TS0 bit7 TS0 bit6 TS0 bit5 TS0 bit4 TS0 bit3 TS0 bit2 TS0 bit1 TS0 bit0 TS1 bit7 TS31 bit0 TS0 bit7 TS0 bit6 TS0 bit5 TS0 bit4 TS0 bit3 TS0 bit2 TS0 bit1 TS0 bit0 TS1 bit7 FSC Double Data Rate DCL Frame Start DCL DD0/1 DU0/1 TS31 bit0 TS0 bit7 TS0 bit6 TS0 bit5 TS0 bit4 TS31 bit0 TS0 bit7 = Upstream Sampling TS0 bit6 TS0 bit5 = FSC Sampling TS0 bit4 Figure 36 IOM-2 Interface Timing in Single/Double Clock Mode 4.3.2.6 IOMU Serial Data Processing The IOMU serial data processing is according to the IOM-2 specifications. Incoming serial data is converted into parallel bytes, and stored in the I-buffer input blocks. The sequence for every time slot received is from MSB (bit 7) to LSB (bit 0). Transmission is performed in the opposite direction, from MSB (bit 7) to LSB (bit 0). 4.3.2.7 IOMU Parallel Data Processing The data read from the IOMU frame buffers by the DSP always reside in the low byte of the 16-bit word. The high byte of the read word is driven by the 8-bit IOMU Data Prefix Register (IDPR). The data prefix is used to accelerate the A-/-law to linear conversions (refer to Chapter 4.5). Note: Any octet written by the DSP to any location in the IOMU frame buffers should reside in the low byte (8 LSB). The high byte of the written word is "don't care". Data Sheet 101 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.3.2.8 IOM-2 Push-Pull and Open-Drain Modes The IOM-2 ports can be configured to Push-Pull or Open-Drain modes by a dedicated bit in the IOMU Control Register. When programmed to Open-Drain, DD0/DD1 is tristated when a `1' is supposed to be transmitted, or during a time slot quadruplet with the associated Tri-State Register bit set. In both cases the external pull-up resistor, which is used when working in open-drain mode, will "pull" the value to `1'. Note: When the IOMU is programmed to 1x 64 time slots per frame mode, DD1 is tristated, independently of the IOM-2 interface push-pull or open-drain mode. DELIC IOMU ITSR DD0 downstream0 data mux DD1 mux downstream1 data Figure 37 IOM-2 Interface Open-Drain Mode DELIC DD0 downstream0 data IOMU ITSR mux DD1 mux downstream1 data Figure 38 Data Sheet IOM-2 Interface Push-Pull Mode 102 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.3.2.9 Support of DRDY Signal from QUAT-S The DRDY input is used when connecting an Infineon QUAT-S transceiver to the DELIC via the IOM-2 interface. It is driven by the QUAT-S to inform the DELIC when a Dchannel is occupied by another S-interface device. The IOMU supports the synchronous DRDY mode, i.e. the QUAT-S is operated in LT-T mode. In this mode, the DRDY signal is valid only during the D-channels. DRDY = `0' means STOP (ABORT HDLC message), and DRDY = `1' means GO. FSC IOM-2 ch 7 IOM-2 ch 0 B1 B2 MON D IOM-2 ch 1 B1 B2 MON D IOM-2 ch 2 B1 B2 MON D IOM-2 ch 3 B1 B2 MON D DU0 DRDY B1 B2 MON D go go = not valid stop stop stop Figure 39 DRDY Signal Behavior IOMU DRDY support features: * Sampling DRDY only once every D-channel at the first bit. * Sampling with the first DCL falling edge (in single data-rate DCL mode) or with the second falling DCL edge (in double data-rate DCL mode), refer to Figure 40. * DRDY support via IOM-2 port 0 only (with a constant delay of one 8 kHz frame) * The status of the DRDY line can be read from register IDRDYR First bit of a D-channel second bit of a D-channel DU0 DRDY D0 valid D1 Sample point of DRDY in single data-rate DCL mode Single Data-Rate DCL Sample point of DRDY in double data-rate DCL mode Double Data-Rate DCL Figure 40 DRDY Sampling Timing Note: If DRDY is not used, DRDY has to be set to 'high'. Data Sheet 103 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.4 PCM Unit PCM Interface Features The PCMU enables the DSP to control the 4 PCM ports. The DSP accesses the incoming PCM time slots, and prepares the outgoing PCM time slots. In general, the PCMU enables the DSP to switch time slots from PCMU to PCMU, IOMU and TRANSIU. The basic structure and programming model of the PCMU is similar to the IOMU. However, the PCMU provides the double capacity of the IOMU. Thus it may handle up to 4 PCM ports and an overall of 128 time slots per frame in the receive direction and 128 time slots per frame in the transmit direction. The following PCMU data rate modes are available: * * * * Four streams of 2.048 Mbit/s each (single and double clock) Two streams of 4.096 Mbit/s each (single and double clock) One stream of 8.192 Mbit/s (single and double clock) One stream of 16.384 Mbit/s (single clock). It is programmable, whether the first or the second 128 time slots of the 8 kHz frame are handled in the PCMU. Note: Other data rates, e.g. 3 x 8.192 Mbit/s are possible by a firmware change. This is realized by assigning DSP data memory to the PCMU. Tri-state control is performed via pins TSCn, programmable per time slot and port. Data Sheet 104 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.4.1 PCMU Functional and Operational Description PCM interface PDC, PFS TSC2 TSC3 PCM Unit IOM Unit MUX RXD0, TXD0, TSC0 RXD1, TXD1, TSC1 RXD2, TXD2 RXD3, TXD3 HDLC Unit GHDLC Unit DSP OAK+ TRANSIU Memory Figure 41 PCMU Integration in DELIC The PCM-unit signals share port pins with the GHDLC-unit. A multiplexer controlled by register MUXCTRL allows to define the required functionality. 4.4.1.1 Frame-Wise Buffer Swapping The main task of the PCMU is the serial-to-parallel conversion of incoming data to a parallel data format (and vice versa) which is directly read by the DSP. This access is required for the DSP to perform switching. The data conversion in the PCMU is done by frame-wise swapping based on a circular buffer structure (see also Figure 35). During each 8 kHz frame one buffer is assigned to the PCMU (I-buffer) and the other one to the DSP (D-buffer). At the end of every frame the buffers are swapped. 4.4.1.2 DSP Inaccessible Buffer (I-buffer) The logical partitioning of each frame buffer into input and output blocks is determined according to the requested data rate as shown in the table below. Data Sheet 105 2003-07-31 PEB 20570 PEB 20571 Functional Description Table 33 Data Rate in0 related port 4 x 2.048 Mbit/s 2 x 4.096 Mbit/s 1 x 8.192 Mbit/s 1 x 16.384 Mbit/s RXD0 00H - 1FH 00H - 3FH 00H - 7FH 00H - 7FH I-Buffer Logical Memory Mapping of Input Buffers Input Blocks in1 RXD1 20H - 3FH in2 RXD2 40H - 5FH 40H - 7FH in3 RXD3 60H - 7FH - Table 34 Data Rate I-Buffer Logical Memory Mapping of Output Buffers Output Buffer Blocks out0 out1 TXD1 A0H - BFH out2 TXD2 C0H - DFH C0H - FFH out3 TXD3 E0H - FFH TXD0 80H - 9FH 80H - BFH 80H - FFH 80H -FFH related port 4 x 2.048 Mbit/s 2 x 4.096 Mbit/s 1 x 8.192 Mbit/s 1 x 16.384 Mbit/s Note: In 1 x 16.384 Mbit/s only the first half of the frame is saved in the buffer 4.4.1.3 DSP Accessible Buffer (D-Buffer) The D-buffer is mapped to a fixed DSP address space. Every DSP access to the D-buffer space is directed automatically to the appropriate sub-buffer. E.g. time slot 32 can be accessed at address 0xA020 in receive and 0xA0A0 in transmit direction. Table 35 Data Rate in0 related port 4 x 2.048 Mbit/s 2 x 4.096 Mbit/s 1 x 8.192 Mbit/s RXD0 DSP Access to D-Buffer Input Blocks Input Buffer Blocks in1 RXD1 in2 RXD2 in3 RXD3 A000H - A01FH A020H - A03FH A040H - A05FH A060H - A07FH A000H - A03FH A040H - A07FH A000H - A07FH 106 - 2003-07-31 1 x 16.384 Mbit/s A000H - A07FH Data Sheet PEB 20570 PEB 20571 Functional Description Table 36 Data Rate out0 related port 4 x 2.048 Mbit/s 2 x 4.096 Mbit/s 1 x 8.192 Mbit/s TXD0 A080H - A09FH A080H A0BFH A080H - A0FFH DSP Access to D-Buffer Output Blocks Output Buffer Blocks out1 TXD1 A0A0H A0BFH out2 TXD2 A0C0H A0DFH A0C0H A0FFH out3 TXD3 A0E0H - A0FFH - 1 x 16.384 Mbit/s A080H - A0FFH Note: In 1 x 16.384 Mbit/s only the first half of the frame is saved in the buffer. 4.4.1.4 * * * * PCMU Interface Data Rate Modes The PCMU may support different serial data rates: up to 4 ports with 2048 Mbit/s (32 time slots per frame) up to 2 ports with 4.096 Mbit/s (64 time slots per frame) 1 port with 8.196 Mbit/s (128 time slots per frame) 1 port with 16.384 Mbit/s (only 128 time slots of the frame are supported) The PCMU circular buffer may handle up to 128 time slots per frame. Thus, when e.g. configured in 4.096 Mbit/s mode, only PCM port 0 and 2 are used. In this case PCM port 1 and 3 remain in IDLE mode, i.e. the TXD1, TXD3 output pins are tri-stated. For the data rate modes up to 8.192 MBit/s, single rate Data Clock (PDC) or double rate Data Clock may be selected. For 16.384 MHz mode only single clock is supported. Single Data Rate PDC Mode * Serial transmission via TXDn with every DCL rising edge * Sampling of the incoming serial data (RXDn) with every PDC falling edge * Sampling PFS with every PDC falling edge. Sampling of PFS = 1 after sampling of PFS = 0 is considered to be the start of a frame. Double Data Rate PDC Mode * * * * Two PDC cycles per bit (the bits are aligned to the frame start) Serial transmission via TXDn with every second PDC rising edge. Sampling of incoming serial data (RXDn) with the second PDC falling edge of each bit. Sampling of PFS every PDC falling edge. Sampling of PFS = 1 after sampling of PFS = 0, is considered to be the start of a new frame. 107 2003-07-31 Data Sheet PEB 20570 PEB 20571 Functional Description Figure 36 shows the PCM interface timing with single and double rate PDC. Single Data Rate PDC Frame Start PFS PDC TXD RXD TS31 bit0 TS0 bit7 TS0 bit6 TS0 bit5 TS0 bit4 TS0 bit3 TS0 bit2 TS0 bit1 TS0 bit0 TS1 bit7 TS31 bit0 TS0 bit7 TS0 bit6 TS0 bit5 TS0 bit4 TS0 bit3 TS0 bit2 TS0 bit1 TS0 bit0 TS1 bit7 PFS Double Data Rate PDC Frame Start PDC TXD RXD TS31 bit0 TS0 bit7 TS0 bit6 TS0 bit5 TS0 bit4 TS31 bit0 TS0 bit7 = data Sampling TS0 bit6 TS0 bit5 = PFS Sampling TS0 bit4 Figure 42 IOM-2 Interface Timing in Single/Double Clock Mode 4.4.1.5 PCMU Serial Data Processing The incoming serial data is converted into parallel bytes, and stored in the I-buffer input blocks. The sequence for every time slot received is from MSB (bit 7) to LSB (bit 0). Transmission is performed from MSB (bit 7) to LSB (bit 0). 4.4.1.6 PCMU Parallel Data Processing The data read from the PCMU frame buffers by the DSP always reside in the low byte of the 16-bit word. The high byte of the read word is driven by the 8-bit PCMU Data Prefix Register (PDPR). The data prefix is used to accelerate the A-/-law to linear conversions (refer to Chapter 4.5). Any octet written by the DSP to any location in the PCMU frame buffers should reside in the low byte (8 LSB). The high byte of the written word is "don't care". Data Sheet 108 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.4.1.7 PCMU Tri-state Control Logic There are eight 16-bit tri-state control registers in the PCMU. Each bit determines whether its associated time slot is valid or invalid. * '0' = the controlled time slot is invalid * '1' = the controlled time slot is valid The tri-state bits control the data transmit pins TXD0 - TXD3. A special set/reset write method is used for updating the tri-state control registers. Every tri-state control register is mapped to 2 addresses: the first is used for set operation, the second for reset operation. Both addresses may be used for read operation. * Set operation: This operation is executed during DSP write access to the set address of one of the TSC registers. The bits in the TSC register are set to '1' according to the bits in the written word. The other bits maintain their value. * Reset operation: This operation is executed during DSP write access to the reset address of one of the TSC registers. The bits in the TSC register are reset to '0' according to the bits in the written word. The other bits maintain their value. The Tri-state Control Registers (PTS0-7) can be accessed by the DSP. Every bit of them controls the TSC signal of one of the 4 PCM ports, for one time slot. The time slot and the port controlled by every bit depend on the data rate mode. In 1 x 256 TS/frame, it depends also on the selected half of the frame. Each TSC signals controls directly its respective TxD port, and is also driven outward via the corresponding TSCn output pin. For the 4 x 32 time slot per frame mode, the next table depicts which port is controlled by each TSC register, and during which time slot. Bit 0 of each TSC register controls the first time slot of the listed time slot range, bit 1 controls the second one etc. Table 37 Time Slots 0..15 16..31 PCM TSC in 4 x 32 TS Mode (4 x 2 MBit/s) TSC0 PTSC0 PTSC1 TSC1 PTSC2 PTSC3 TSC2 PTSC4 PTSC5 TSC3 PTSC6 PTSC7 In 2 x 64 time slot per frame mode, only PCM ports 0 and 2 are used. TSC1 and TSC3 are permanently '0' (all time slots are invalid). Table 38 Time Slots 0..15 16..31 32..47 48..63 Data Sheet PCM TSC in 2 x 64 TS Mode (2 x 4MBit/s) TSC0 PTSC0 PTSC1 PTSC2 PTSC3 TSC1 inactive inactive inactive inactive 109 TSC2 PTSC4 PTSC5 PTSC6 PTSC7 TSC3 inactive inactive inactive inactive 2003-07-31 PEB 20570 PEB 20571 Functional Description In 1 x 128 time slot per frame mode, only PCM port 0 is used. TSC1, TSC2 and TSC3 are permanently '0' (all time slots are invalid). In 1 x 256 time slot per frame mode, only one half of the frame is used. All TSC pins are permanently '0' during the other half of the frame. Table 39 Time Slots 0..15 16..31 32..47 48..63 64..79 80..95 96..111 112..127 PCM TSC in 1 x 128 TS (1 x 8 MBit/s) and 1 x 256 TS (1 x 16 MBit/s) (1st Half) Mode TSC0 PTSC0 PTSC1 PTSC2 PTSC3 PTSC4 PTSC5 PTSC6 PTSC7 TSC1 inactive inactive inactive inactive inactive inactive inactive inactive TSC2 inactive inactive inactive inactive inactive inactive inactive inactive TSC3 inactive inactive inactive inactive inactive inactive inactive inactive Note: The same structure applies to the 256 TS per frame (first frame half) mode, except that all time slots (0..127) are transmitted in the first half of the 8 kHz frame. Table 40 Time Slots 0..127 128..143 144..159 160..175 176..191 192..207 208..223 224..239 240..255 PCM TSC in 1 x 256 TS (1 x 16 MBit/s) (2nd Half) Mode TSC0 inactive PTSC0 PTSC1 PTSC2 PTSC3 PTSC4 PTSC5 PTSC6 PTSC7 TSC1 inactive inactive inactive inactive inactive inactive inactive inactive inactive TSC2 inactive inactive inactive inactive inactive inactive inactive inactive inactive TSC3 inactive inactive inactive inactive inactive inactive inactive inactive inactive Note: Concerning the behavior of PCM output driver also see "PCM Output Driver Anomaly" on Page 286 Data Sheet 110 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.5 A-/-law Conversion Unit The A-/-law Unit performs a bi-directional conversion between a linear representation of voice data and its companded representation (according to A-law or -law). The conversion is applicable on all B-channels via IOM-2, IOM-2000 or PCM. IOMU Switch PCMU ing IOM-2000 DSP Conversion A/-law Unit Input FF A -law to Linear 256 Linear to A/-law Logic Circuit -law to Linear 256 Output FF 16 Figure 43 Data Sheet ROM A/-law Unit Integration 111 2003-07-31 PEB 20570 PEB 20571 Functional Description A-/-law to Linear Conversion The conversion is done via a 512 x 16 ROM table. The low 256 bytes translate the A-law value into linear, while the high 256 words translate the -law to linear. The DSP issues a read cycle, in which the 8 MSBs of the 16-bit address represent the ROM table address, and the 8 LSBs are the actual value which is to be converted. The converted linear value is the contents read from the ROM. Note that no wait states are required for this direction of conversion. A-law values in the ROM are stored in the 13 MSBs. The 3 LSBs are always '0'. The law values in the ROM are stored in the 14 MSBs. The 2 LSBs are always '0'. Linear to A-/-law Conversion The conversion is done by dedicated hardware. The DSP programs the control register to perform either A-law or -law conversion. The linear value is written into the Input register (AMIR), and the A-law or -law value is read from the Output register (AMOR). Note that this is only possible one cycle later. Data Sheet 112 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.6 4.6.1 HDLC Unit HDLC Overview High-level data link control (HDLC) is a most common protocol in the data link layer, layer 2 of the OSI model. Signalling protocols LABD and LAPB are based on HDLC and its framing structure: Opening Flag, Address Field, Control Field, Data Field, CRC, Closing Flag, Interframe Timefill. HDLC uses a zero insertion/deletion process (bit-stuffing) to ensure that a data bit pattern matching the delimiter flag (01111110 = 7EH) does not occur in a field between the starting and the closing flag. The HDLC frame is synchronous. An address field is needed to carry the frame's destination address because the frame can be sent to different systems. An address field can be 8, or 16 bits long, depending on the data link layer protocol. LAPB uses an 8-bit address, LAPD 16-bit address. The length of the data in the data field depends on the frame protocol. Error control is implemented by appending a cyclic redundancy check (CRC) to the frame, which is 16 bits long. The multichannel HDLC controller within the DELIC consists of two parts: a hardware block (HDLC Unit) and a dedicated on-chip processor (OAK DSP). The processor handles the HDLCU by writing/reading signalling data and reacts on slow events by software. The following table shows the main HDLC features and the responsible unit for its handling: HDLC Features Flag detection and generation Zero insertion/deletion (bit stuffing) 16-bit CRC-CCITT generation and checking Time slot assignment (2- or 16-bit) Programmable flags between successive frames Flexible address handling Flexible buffers management (per frame) Separate interrupts for frames and buffers (Rx and Tx) Flag/abort/idle generation and detection Detection of non-octet aligned frames Automatic retransmission in case of collision HDLC Unit X X X X Processor X X X X X X X X X Note: The multichannel HDLC Unit is not connected to any DELIC pin. Data Sheet 113 2003-07-31 PEB 20570 PEB 20571 Functional Description The HDLC automatically recognizes HDLC frames with the following interframe time fill combinations: * n consecutive flags (n = 1, 2, 3,.. ; n = 1 is called shared flag, if the closing flag of one frame is the opening flag of the next frame. n > 1 is also called unshared flag mode.) * m "ones" between the closing flag and the opening flag (even when m = 1 to 5) * corrupted flag between the closing flag and the opening flag The HDLCU may process up to 32 full-duplex HDLC channels in parallel. As it is controlled by the DSP, it is very flexible. The HDLCU includes 32 Receive Input Buffers, 32 Receive Output Buffers, 32 Transmit Input Buffers and 32 Transmit Output Buffers, some HDLC protocol processing logic and a command RAM. DSP D-Buffer* DSP D-Buffer* * Frame-buffers of the IOMU, PCMU or IOM-2000 that belong to the DSP during the present frame 32x8 Receive Input Buffer 32 channels 32x16 Transmit Output Buffer 32 channels encoded decoded Internal Processing command RAM Internal Processing Receive Output Buffer 32 channels 32x8 32x8 32x8 Transmit Input Buffer 32 channels DSP data double buffer Figure 44 DSP Control DSP Data Double Buffer HDLCU General Block Diagram Figure 44 shows the HDLCU structure. Each buffer, except the Transmit Output Buffer, is 1 Byte small, hence one byte is assigned to each HDLC channel per direction. The Transmit Output Buffer is 2 Bytes as it also contains a 7-bit status vector assigned to the channel. Data Sheet 114 2003-07-31 PEB 20570 PEB 20571 Functional Description The DSP assigns each time slot used for transmitting an HDLC message to a different address in the Receive/Transmit Input Buffers. The HDLCU decodes/encodes the time slots into the corresponding addresses in the Receive/Transmit Output Buffers. During every frame, two HDLCU activities are performed: 1. DSP access to the HDLCU 2. HDLCU encoding/decoding At the beginning of a frame the DSP checks if the HDLCU is busy (HHOLD = '0'). Note: The DSP may only access the buffers and command RAM when DSPCTRL = `1'. In the receive direction the DSP places HDLC message time slots to be processed from the D-buffers into the Receive Input Buffer. Processed message time slot octets may be read by the DSP from the Receive Output Buffer. In the transmit direction the DSP places HDLC message time slots to be processed in the Transmit Input Buffer. Processed time slots may be read from the Transmit Output Buffer and placed into the D-Buffer of the IOMU, PCMU or TRANSIU from which they will be transmitted during the next frame. 4.6.2 4.6.2.1 HDLCU Operation Initialization of the HDLCU The DSP first resets the receive and transmit mechanisms of all HDLC channels. 1. The DSP requests the External Controller for HDLCU setup. 2. The DSP sets the bit DSPCTRL to `1'. 3. The DSP resets the receive mechanism and transmit mechanism of a channel by setting the RECRES flag of its command vector to `1' and inserting an abort command. The DSP also writes the setup of the HDLCU. 4. The DSP sets DSPCTRL to `0'. 5. When the HDLCU finishes processing (HHOLD = '1'), the HDLCU is initialized and is ready for use. 4.6.2.2 Transmitting a Message The DSP must place a Start transmission command at the appropriate address in the command RAM. If CRC encoding is required, the DSP must set bit 1 to `1' in the command vector. After the first flag has been transmitted, the HDLC starts to transmit the message. In shared flag mode the HDLCU starts transmitting the message in the frame adjacent to the reception of the Start transmission command. Note: Messages with zero byte data content are not supported. Data Sheet 115 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.6.2.3 Ending a Transmission When placing the last octet of the message into the Transmit Input Buffer, the DSP places an End transmission command in place of the Start transmission command without changing the CRC bit. If CRC encoding is required, the CRC vector will be transmitted bit by bit after the octet of the message, and then a flag will be transmitted. If CRC encoding is not required, a flag will be transmitted directly after the last octet of the message. 4.6.2.4 Aborting a Transmission In order to abort transmission of a message over a dedicated channel, the DSP places an abort command in the appropriate address in the command RAM. The message being transmitted over the channel is aborted and 'ones' are transmitted over the channel instead (even in shared flag mode). 4.6.2.5 DSP Access to the HDLCU Buffers Reading a channel from the Receive Output Buffer and writing to a channel in the Transmit Input Buffer is done according to the channel status vector and according to the Empty and Full procedures as shown below: Empty procedure * If the EMPTY flag of a channel is set by the HDLCU to `1', then move a new time slot to be transmitted from the pipe to the Transmit Input Buffer. * If the pipe is empty change the pipe page and ask for the next 8 bytes of data from the external controller by means of DMA or transfer ready indication. Note: The B-channel buffer may be emptied within a single frame, while it takes at least 4 frames to empty a D-channel buffer. Full procedure * If the FULL flag of a channel is set by the HDLCU to `1' then the DSP moves the time slot from the Receive Output Buffer into the double buffer. * If the pipe is full change the pipe page and transfer the next 8 bytes of data to the External Controller by means of DMA or transfer ready indication. Note: The B-channel buffer may be filled within a single frame, while a D-channel buffer will take at least 4 frames to fill. 4.6.3 Functionality The multichannel HDLC controller can be assigned to any timeslot on any time-division multiplexing (TDM) port: IOM-2, PCM and TRANSIU. Data Sheet 116 2003-07-31 PEB 20570 PEB 20571 Functional Description In receive direction, the processor fetches the D-channel (16 kbit/s signalling) or the Bchannel (64 kbit/s) from the assigned timeslot and writes it into the corresponding channel register of the HDLC Unit. After the HDLC Unit encoded the data (e.g. performed bit stuffing), the processor reads ready data and stores it in the receive buffer in on-chip memory. The data flow is shown in the following figure. DP RAM with IOM-2 or PCM structure D B1 B2 MON C/I B1 B2 MON D C/I M M IOM-2 / PCM S/P DP RAM DSP Data Memory 1. Rx Buffer Page 1 e.g. 8 Byte Rx Buffer Page 2 e.g. 8 Byte HDLC Unit HDLC Channel_n ("O", Flag, CRC) Receive Input Buffer Receive Output Buffer DSP 2. 3. DELIC Maibox P Figure 45 HDLC Data Flow in Receive Direction HDLC-RX The Receive Input and Receive Output Buffers within the HDLCU are 1 Byte per HDLC channel. The main Rx Buffer in DSP RAM is 2 x 8-Byte large per HDLC channel (in the DELIC-LC version). Data Sheet 117 2003-07-31 PEB 20570 PEB 20571 Functional Description The processor handles the HDLCU (tasks 1) during every IOM frame, i.e. every 125 s. If a 16-kbit/s channel is handled, the task 2 is performed about every 4th to 5th frame (4 x 2-bit writing to the HDLCU minus "0-detection" => 8-bit output). At the beginning of a frame, the DSP checks if the HDLCU is busy (HHOLD = '0'). The DSP may only access the buffers and command RAM when DSPCTRL = `1'. In transmit direction, the DSP writes data 8-bit wise into the Transmit Input Buffers, reads the processed data from the Transmit Output Buffers and places the coded data into the assigned destination time slot like in the following example: * 2-bit wise writing into the D-channel of an IOM-2 interface of the IOM Unit, or into the TRANSIU in case of TRANSIU interface, * 8-bit wise writing into a signalling channel of the PCM highway by writing into the PCM Unit. In general, the HDLC controller can handle all 32 HDLC channels at different data rates using any TDM channel: e.g. * * * * 16 kbit/s for D-channel signalling 64 kbit/s for B-channel signalling 8 kbit/s for proprietary signalling (only PB version) 256 kbit/s for data transfer in transparent mode. Data Sheet 118 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.7 4.7.1 GHDLC Unit GHDLC Overview Messages are transceived serially, bit by bit over the line and undergo encoding/ decoding according to the HDLC protocol. A received message is collected bit by bit from the line and stored as octets in the Receive buffer and read by the DSP. A transmitted message which is placed by the DSP as octets in the Transmit buffer, is transmitted bit by bit over the line. The GHDLC (General HDLC) controller works similar to HDLCU (refer to "HDLC Overview" on Page 113). Main features/differences: * it has its own physical interface with the following signal lines: LRxD, LTxD, LTSC, LCxD, LCLK, * it works at a speed of up to 8.192 Mbit/s * it supports also multi master bus * it may work independently from the internal clocking (FSC, PDC,..) using an external clock * the receive/transmit buffer in the GHDLC are 2 x 32 Bytes large, respectively Like the HDLC Controller, the GHDLC Controller consists also of two parts: a hardware block (GHDLC Unit for fast events) and a processor (OAK DSP). Data from the serial input line (LRxD) is processed and stored in the Receive Buffer which is to be read by the DSP. Transmit data is placed by the DSP in the Transmit Buffer, is processed by hardware and transmitted over the serial line (LTxD). . status and interrupt vector DSP Double Buffer DSP Double Buffer Receive Buffer Receive Processing data in from line bit by bit LRxD Transmit Buffer set-up vectors command vector data out to line bit by bit Transmit Processing LTxD Figure 46 Data Processing in the GHDLC 4.7.2 GHDLC General Modes of Operation Each GHDLC channel has three main modes of operation: * HDLC Mode: In this mode flag-recognition/insertion and zero deletion/addition are performed. CRC decoding/encoding may be performed. Data Sheet 119 2003-07-31 PEB 20570 PEB 20571 Functional Description * Transparent Mode: No HDLC framing exists. In the receive direction everything on the line is automatically passed to the buffer. Each time the buffer is filled an interrupt to the DSP is generated. * Asynchronous Mode: This mode is used with request to send/ clear to send handshaking. In this mode data is transmitted over a channel at a very slow rate of up to 300 baud and controlled directly by the DSP. RTS/CTS Hand-shaking In point to point configuration the LCxD and LTxD are used for CTS and RTS handshaking. A transmission request is indicated by outputting a logical `0' on the request to send output (RTS). After having received the permission to transmit (CTS), the HDLC starts data transmission. If permission to transmit is withdrawn in the course of transmission, the frame is aborted and an idle is sent. 4.7.3 External Configuration and Handshaking in Bus Mode The GHDLC is connected to the following DELIC interface lines: LTSC / RTS LTxD GHDLC LRxD LCxD / CTS LCLK Figure 47 GHDLC Interface Lines Serial data is transceived over the LRxD/LTxD lines. The line clock can be driven by an external GHDLC device or can be generated internally by the PCM clocking path. The selected internal clock is also driven outward via LCLK. 4.7.3.1 External Tri-State in Point-to-Multi-Point Mode LTSC is the external tri-state control line. When LTSC is high LTxD is disabled and in high impedance state. When LTSC is low, LTxD may take on values 0 or 1 when in push pull mode, 0 or high impedance when in open drain mode. 4.7.3.2 Arbitration Between Several GHDLCs Arbitration between several GHDLCs can be done in two ways: * Polling * Collision Detection Data Sheet 120 2003-07-31 PEB 20570 PEB 20571 Functional Description Polling means that the DSP is polled to see if it has anything to send by way of a frame which is actually a question. The GHDLC simply receives this frame and passes it on to the DSP like any other. Note: This mode is not supported by the DELIC-LC. When using Collision Detection many GHDLCs may start transmitting at the same time. Suppose that several GHDLCs start transmitting simultaneously, the first byte transmitted is always a flag which is common to every GHDLC. Afterwards each GHDLC transmits it's address which is, of course, unique to each GHDLC. When a difference is discovered between the transmitted bit (LTxD) and the collision bit (LCxD), the transmission is aborted. The GHDLC will try to send the message again after it has detected the bus to be idle for a specified time, according to it's class. Arbitration on a line is such that the GHDLC channel with the lowest address gets the highest priority. All the GHDLC channels are divided up into two groups: classes 8, 9 and classes 10, 11. Initially the DSP programs each channel to be either class 8 or 10. If during transmission a bit collision occurs the GHDLC will have to count 8 consecutive ones (in class 8) or 10 consecutive ones (in class 10) before it tries to retransmit. After a certain GHDLC channel succeeds in making a full transmission it's class is increased by 1 to 9 or 11 so that if a bit collision occurs the GHDLC channel will have to count more ones before retransmitting. After the GHDLC channel has counted 9 or 11 consecutive ones it's class is brought back down to it's former level (see ITU-T 1.430 section 6.1.4). Collision Detection in Point-to-Multi Point Configuration The GHDLC can perform a bus access procedure and collision detection. As a result, any number of HDLC controllers can be assigned to one physical channel, where they perform statistical multiplexing. When a mismatch between a transmitted bit and the bit on CxD is detected, the GHDLC stops sending further data and an idle is transmitted. As soon as it detects the transmit bus to be idle again, the GHDLC automatically attempts to re-transmit its frame. The DSP programs the HDLC its class and the HDLC performs a priority mechanism to detect idle on the line. Data Sheet 121 2003-07-31 PEB 20570 PEB 20571 Functional Description TxD CxD RxD TxD CxD RxD Group Controller DSP HDLC TxD CxD RxD Figure 48 Point-to-Multi Point Bus Structure If a Txd and CxD difference occur, the HDLC aborts its transmission, generates an interrupt for the DSP reporting the collision and disables the output of TxD (High Impedance or `1' programmable selecting). The HDLC automatically restarts transmission when the bus is detected to be idle again. The HDLC detects idle if CxD was `high' for (8 + 2*Class + D), where Class is a DSP programmable and is 0 for class 1 and 1 for class 2. D is 1 between a success transmission and idle detection on the bus. 4.7.4 GHDLC Memory Allocation The memory in the GHDLC is build by a 128 x 8 bit RAM equally divided between the GHDLC and the DSP. The GHDLC has a receive buffer and a transmit buffer, divided into two blocks. One block is allocated to the GHDLC channel in the receive direction, the other block is read by the DSP. Similarly in the transmit buffer, one block is allocated to the GHDLC channel in the transmit direction, the other block is written to by the DSP as shown in Figure 49. Note that the GHDLC has higher priority for the buffer access, whereas the DSP is able to read and write the RAM at a much higher frequency. The DELIC contains 4 GDLC Controllers. If only one GHDLC Controller is used, the visible buffer size is 32 bytes for each direction, for two channels 16 bytes per channel and for 4 channels 8 bytes per channel. Memory is allocated to each receive and transmit buffer according to the number of used channels by the following table: Data Sheet 122 2003-07-31 PEB 20570 PEB 20571 Functional Description Receive Buffer Block 0 one channel two channels 32 bytes 16 bytes Block 1 32 bytes 16 bytes 8 bytes Transmit Buffer Block 0 32 bytes 16 bytes 8 bytes Block 1 32 bytes 16 bytes 8 bytes four channels 8 bytes This leads to the following address configuration: Table 41 No. of Channels 1 channel 2 channels 4 channels GHDLCU Receive Buffer Configuration Direction ch 0 Receive Transmit Receive Transmit Receive Transmit 0x2040 0x2000 0x2040 0x2000 0x2040 0x2000 0x2060 0x2020 0x2070 0x2030 0x2060 0x2020 0x2050 0x2010 Channel Address ch1 ch 2 ch3 In the receive direction, blocks are swapped in two cases: * The receive buffer is full. The swap is issued immediately after the buffer has become full. * An end of a frame indication was detected at the beginning of a frame. The frame is programmable to 62.5 s or 10 s (see Chapter 6.2.6.15). To avoid a loss of data in case of a buffer full indication followed by an end of frame indication, this condition becomes true only if additionally there was no FULL interrupt during the previous frame. In the transmit direction blocks are swapped each time a start transmission command is issued in the command register. Data Sheet 123 2003-07-31 PEB 20570 PEB 20571 Functional Description Receive Buffer DSP read Block Block GHDLC receive Transmit Buffer DSP write Block Block GHDLC transmit Figure 49 GHDLC Receive and Transmit Buffer Structure The GHDLC unit and DSP always read and write to different areas in the RAM. Memory is equally allocated to each of the receive and transmit buffer blocks (32 bytes each). The DSP always writes to the block addresses. The switching between blocks is done internally and does not concern the DSP. 4.7.5 GHDLC Interrupts Full Interrupt: A full interrupt is generated if: * The receive buffer is full. The interrupt is issued immediately after the buffer has become full. * An end of a frame indication was detected at the beginning of a frame. The frame is programmable to 62.5 s or 10 s (Chapter 6.2.6.15). To avoid a loss of data in case of a buffer full indication followed by an end of frame indication, this condition becomes only true if additionally there was no FULL interrupt during the previous frame. Empty Interrupt: An empty interrupt is generated every time a transmit buffer was emptied by the GHDLC. Note: Messages with zero byte data content are not supported. 4.7.6 4.7.6.1 Operational Description GHDLC Initialization The initialization procedure include writing for each HDLC it's configuration to the registers set. The four HDLCs will be arranged according to the specified configuration. Data Sheet 124 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.7.7 GHDLC Protocol Features The following GHDLC features related to HDLC protocol may be selected in HDLC mode: * Collision Detection: May be active or inactive (relates only to the transmit direction) * Flags / Ones Interframe: Flags or Ones are transmitted between each frame and are automatically recognized in receive direction. In transmit direction the GHDLCU can be programmed for either Interframe. * CRC Mode: Two possible settings: 16-bit CRC / No CRC (relates to both the transmit and receive directions, and only when operating in the HDLC mode). * Push-Pull / Open drain: In push pull mode a pin may be driven to `1' or `0'. When in open drain mode a pin may be driven to `0' or high impedance. The GHDLCU is able to receive 'flags' as well as '1' as ITF. If flags are used as ITF the DELIC is able to detect ITF-flags with only one 'Zero' between the 'Ones' (shared '0'). End Flag data End Flag ITF = Flag ITF = Flag Start Flag Figure 50 Interframe Time Fill with shared Zero 4.7.8 GHDLC possible Data Rates for the DELIC-LC/PB The DELIC-LC has one GHDLC channel with a data rate of up to 2.048 Mbit/s. Although the DELIC-PB features 4 GHDLC channels, not all channels are available for each application. If full duplex operation is assumed and if the receive data comes randomly, it's recommended to use not more than two channels with 2 Mbit/s or 1 channel with up to 8 Mbit/s. The reason for this is that the data flow through the P-interface is limited by the Paccess time, the maximum number of interrupts supported by the P and by the DMAaccess time. Assuming a system with 4 x 2 Mbit/s GHDLC ports this would mean a worst case interrupt repetition rate of 12.5 s (i.e. 4 x 32 bytes per direction have to be transmitted via a 32 byte mailbox). Usually the Operating System wouldn't allow such a high interrupt rate. However if the performance requirements can be reduced (e.g. not all channels are active at the same time or the HDLC packet size is small or the packet rate is low) then a system with 4 x 2 Mbit/s might be reasonable with the DELIC. Data rates other than 2.048, 4.096 and 8.192 Mbit/s require an external clock. The DELIC may be configured to use an external clock for each GHDLC port. Data Sheet 125 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.7.9 GHDLC Using external DMA Controller One of the four GHDLC channel of the DELIC-PB can be assigned to the DMA mailbox handled by an external DMA controller. The detailed handling of DMA is described in "DMA Mailbox (DELIC-PB only)." on Page 133. Data Sheet 126 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.8 4.8.1 DSP Control Unit General The DSP Control Unit (DCU) controls the DSP access to DELIC's blocks. It performs the following tasks: * * * * * * DSP program and data address decoding Interrupt handling Data Bus and Program Bus arbitration DSP run time statistics Boot support Emulation support 4.8.2 DSP Address Decoding The DCU decodes the DSP data address bus (DXAP) and the DSP program address bus (PPAP) for performing the following tasks: * Generating the DSP memory mapped register controls, based on decoding of the 8 MSB lines of the data address bus * Generating the GHDLC, TRANSIU, HDLCU, IOMU and PCMU RAM controls * Generating program and data RAM controls upon detection of their address * Generating the read signal for the program ROM 4.8.3 * * * * * Interrupt Handling The following events are reported by the various telecom peripheral blocks to the DSP: GHDLC DMA mailbox P mailbox IOM interface Frame synchronization (FSC) interrupt PCM interface Frame synchronization (PFS) interrupt The GHDLC, DMA Mailbox and Microprocessor Mailbox interrupt sources are assigned to the DSP interrupts (INT0, INT1 and INT2) as shown in Figure 42. The FSC and PFS are reported as status bits (require DSP polling) in the Status Event Register (STEVE). Table 42 Interrupt INT0 INT1 INT2 NMI Data Sheet Interrupt Map Source P DMA Mailbox P General Mailbox FSC & PFS GHDLC 127 2003-07-31 PEB 20570 PEB 20571 Functional Description Note: The NMI interrupt maybe enabled/disabled in the INTMASK register. 4.8.4 DSP Run Time Statistics The DSP run time statistics is used for the DSP work load estimation. By using this HW, the maximum time spent by the DSP from the FSC until the tasks ends may be found. The DSP statistics include an eight bit counter STATC which is counting up every 1s. Reset by FSC of the frame n+1, only if the DSP has read the counter already Counter (in Frame n) 1 s STATC Maximum Value Register STATI DSP Figure 51 Statistics Registers DSP STATC is reset upon FSC rising edge. When the DSP finishes a task, it reads STATC. The time between two consecutive FSC is always 125 s, therefore, if the DSP is working properly, the counter value should always be less then 125 s. If the DSP failed to read the counter value and a new FSC rising edge has arrived, the counter is not reset. Therefore, the DSP reads a value greater then 125. It means that the DSP failed to finish it's tasks within the time frame of 125 s. The STATI register is added for helping the user to perform the statistics. STATI is a general purpose 8-bit read/write register. Data Sheet 128 2003-07-31 PEB 20570 PEB 20571 Functional Description The user program should perform statistics in the following way: * The STATC is reset upon detection of FSC rising edge. * The DSP finishes its activities and reads the value of STATC and STATI. The DSP compares STATC to the previous maximum value saved in STATI. * If the new value is larger, it is written to STATI. The system programmer can get the counter value via P Mailbox and thus can change the DSP program. 4.8.5 Data Bus and Program Bus Arbitration The internal data bus (GEXDBP) and program data bus (GIP) are tri-state buses. Since these buses must never float, the DCU keeps track of the bus activities. If during a dedicated cycle no driver is on the bus, the DCU puts a default value on the bus. 4.8.6 Boot Support The P boot is the process which loads the external P program RAM via the P Mailbox into the on-chip DSP program RAM. The boot is controlled by a boot routine residing in the internal DSP program ROM. This routine is started upon DELIC reset according to the BOOT strap pin status. The second boot option is the emulation boot, which loads the monitor (BI routine) to the program RAM. This routine enables the PC emulator to control the DSP. At system start-up the program code for the DSP is transferred into the internal RAM from the external P. The contents for the program and data boot is delivered in a so called HEX file. The code format of the HEX file is the following: Code,:,16 bit address, 16 bit opcode C:0000 4180 C:0001 0018 C:0004 4180 C:0005 00BA C:0006 4180 C:0007 00BD C:000E 4180 C:000F 00BE ... The program boot starts with the "Start Loading Program RAM" command which is coming from the DELIC boot routine. OCMD = 0x1F This command must be polled from the P because the interrupt is still not activated. The P confirms this with the "Start Boot" command. MCMD = 0x55 Data Sheet 129 2003-07-31 PEB 20570 PEB 20571 Functional Description The program code is now transferred in pieces of maximum 15 words by use of the "Write Program Memory Command". MDT0 = 0xDESTINATION_ADDRESS MDTn = 0xOPCODE_WORDn MCMD = 0xAn[n=1..15 number of code words to write to address++] Before writing this command, the P must check that the mailbox is free. This is done by reading the MBUSY bit (bit 7 of address 0x41). The P must wait until this bit is reset before sending the next command. Missing addresses in the HEX file must not be loaded. The "Write Program Memory Command" must be repeated until the program code is fully loaded. The end of the code segment inside the HEX file is the change from C: (code) to D: (data). This is the start of the data segment, which is needed for the Data Boot, described in the next step. After all the code has been loaded, the "Finish Boot" command must be sent: MCMD = 0x1F 4.8.7 Reset Execution and Boot Strap Pin Setting The reset is executed via low signals on the DELIC RESET pin (29) and the VIP RESET pin (44). It is recommended to connect the VIP RESET inputs to the DELIC RESIND output pin (89). The RESIND signal is a delayed reset signal and stays at least 500 us after termination of the DELIC RESET input. This mechanism ensures that all output clocks of the DELIC have become stable even after a short reset was applied. Connecting the VIP reset to this RESIND signal ensures stable VIP clocking after reset (Layer1 clock, DCL2000, FSC). Together with applying the reset signal to the DELIC, the strap pin signals must be defined. There are 9 pins at the DELIC device which have a special functionality. These so called strap pins are used as inputs while reset is active and determine different modes like master/slave mode of the PCM interface, test modes, boot mode,... Please refer to page 38 for detailed information about the strap pin options. The settings of the strap signals are sampled with the rising edge of the DELIC RESET input signal. For a P- boot, the default settings of strap 4 (emulation boot) and strap 6 (boot strap) are needed. After a correct reset execution and strap pin setting, the DELIC sends the command "Start Loading Program RAM" to the uP: OCMD = 0x1F Data Sheet 130 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.9 4.9.1 General Mailbox Overview The P and the DSP communicate via a bidirectional Mailbox according to the mailbox protocol described in DELIC-LC/-PB Software User's Manual. The DELIC provides two dedicated Mailboxes that may be used in two operational modes: * DMA mode in which the two Mailboxes operate independently, one serves as a general purpose Mailbox and the other serves as a DMA Mailbox. * Expanded Mailbox mode in which the two Mailboxes are regarded as a enlarged general purpose Mailbox, providing a double number of registers. The general purpose Mailbox includes two separate parts: * P Mailbox - enables transfers from the P to the OAK. * OAK DSP Mailbox - enables transfers from the OAK to the P. Both parts include a command register, 9 x (16-bit) registers (17 registers in expanded mode) and a busy bit. One of the data registers in every part has a special addressing mode, i.e. the OAK may access either a certain byte of a word or the whole word which is temporarily stored in the Mailbox. This requires to use 3 different addresses in OAK's direction. Note: The Mailbox protocol commands structure is described in DELIC-LC/-PB Software User's Manual. 4.9.2 * * * * P Mailbox The P Mailbox includes: Eight 16-bit data registers (MDTn) A16-bit general register (MGEN) An 8-bit command register (MCMD) A 1-bit busy register (MBUSY) Registers MDTn, MGEN and MCMD may be written by the P and read by the OAK. The MBUSY register may be written by the DSP and read by the P. A write of the P to the MCMD-register of the P-mailbox generates an interrupt to the OAK. Thus, the user has to provide all mailbox data prior to writing to register MCMD. The MBUSY bit which may be read by the P (register MBUSY) is set automatically after a write to the P command register (MCMD) and reset automatically by a direct OAK write operation to it. Note: The command Opcodes are defined in DELIC-LC/-PB Software User's Manual. Data Sheet 131 2003-07-31 PEB 20570 PEB 20571 Functional Description Data Transfer from the P to the OAK * The P reads the busy bit and checks whether the Mailbox is available (MBUSY='0') * The P writes to the Data registers MDTn (optional) * The P writes to the P Command register (MCMD), this write must be performed and sets automatically the P Mailbox busy bit (MBUSY). * An OAK interrupt (INT2) is activated due to the write to the Command register (MCMD). * The OAK INT2 routine reads MCMD and performs the command (the read of the command register resets the INT2 activation signal). * When finished, the INT2 routine resets MBUSY for enabling the P to send the next command. Note: The P may perform consecutive writes to the P Mailbox, and the user must guarantee that the data has been transferred to the OAK correctly (the busy bit has been reset) before writing new data to the P Mailbox. 4.9.3 * * * * OAK Mailbox The OAK Mailbox includes: Eight 16-bit data registers (ODTx) A 16-bit general register (OGEN) An 8-bit command register (OCMD) A 1-bit busy register (OBUSY) Registers ODTx, OGEN and OCMD may be written by the OAK and read by the P. The OBUSY bit may be written by the P and read by the OAK. In addition, the P can read this bit (because the P could poll this bit). A write of the OAK to register OCMD of the OAK mailbox generates an interrupt to the P. Thus the OAK firmware provides all mailbox data prior to writing to register OCMD. The OBUSY- bit which can be read by the OAK, is set automatically after a write of the OAK to register OCMD and is reset by a direct P write to it (when the P has finished reading the OAK Mailbox contents). Note: The Opcodes indications are defined in DELIC-LC/-PB Software User's Manual. Data Sheet 132 2003-07-31 PEB 20570 PEB 20571 Functional Description Data Transfer from the OAK to the P * The OAK reads the busy bit and checks whether the MB is available (OBUSY='0') * The OAK writes to the data registers ODTn (optional) * The OAK writes to the command register (OCMD). This write must be performed and automatically sets the OAK Mailbox busy bit (OBUSY) * A P interrupt is activated due to the write operation to the register OCMD. * The P reads the command register and performs the command. * When finished, the P resets OBUSY for enabling the OAK to send the next command. Note: The OAK may perform consecutive writes to the OAK Mailbox and the OAK firmware guarantees that the data has been transferred to the P correctly (OBUSY reset) before writing new data to the OAK Mailbox. 4.10 DMA Mailbox (DELIC-PB only). The DELIC provides two dedicated mailboxes that may be used in two different ways: 1. In DMA mode, one may be used as a DMA mailbox (16 bytes) and one as general purpose mailbox (16 bytes). Both mailboxes operate independently. 2. In Expanded Mailbox mode, the two mailboxes are regarded as one large general purpose mailbox, providing double number of registers (32 bytes). The mailbox mode can be configured in the configuration register (MCFG:DMA). The 16-byte deep DMA mailbox connects the DELIC and an external DMA controller. The DMA mailbox can be accessed only by the DMA controller and only upon a request from DELIC. Note: The P can not access the DMA mailbox. It can access directly only the General Mailbox. The DMA mailbox can be used for different data transfers, e.g.: * * * * Data transfer via GHDLC (e.g. 2 Mbit/s) Transfer of D-channel signaling data (16 kbit/s) Recording and replay of voice channels (64 kbit/s) Fast data transfers between external and DELIC internal memories The DMA mailbox consists of two separate parts: * Transmit mailbox - for DMA data transfer from memory to DELIC. * Receive mailbox - for DMA data transfer from DELIC to memory. In order to transmit data, the DELIC must initiate a DMA Request for Transmit data (DREQT); for receiving data, it initiates DREQR. The DMA controller answers with DMA Acknowledge (DACK) signal together with RD or WR signal (Intel/Infineon bus type), or R/W and DS (Motorola bus type). Which signals are used depends on the selected Data Sheet 133 2003-07-31 PEB 20570 PEB 20571 Functional Description DMA mode, and the data transfer direction. Two DMA modes are supported: * Two-cycle DMA transfer mode called also Memory-to-memory mode * Single cycle DMA transfer mode called also Fly-by mode An example for a two-cycle DMA transfer in receive direction (data is read from DELIC and written to memory) in Intel/Infineon Mode is shown in Figure 52. Memory 1. cycle DMA Controller DREQR DMA Mailbox Memory 2. cycle WR DACK + RD Data Bus Data DMA Controller ADDR Data Data Bus DMA Mailbox 2-Cycle-Mode DELIC DELIC Figure 52 Two-cycle DMA Transfer Mode for Receive Direction 1. The DMA mailbox contains data (the receive mailbox contains up to 16 bytes of data) 2. DELIC requests DMA service via DREQR 3. DMA controller issuses a DMA Acknowledge (DACK) signal for addressing the DMA mailbox and a "read" signal for indicating DELIC that it will read the receive mailbox 4. The DMA controller reads the data into an on-chip register (= end of first cycle). 5. The DMA controller writes the data into the memory using ADDR and WR (= second cycle). The main advantage of the two-cycle DMA transfer mode, compared to general mailbox access by a P, is its faster response time (depends on the operating system) and a simple data flow control. Data Sheet 134 2003-07-31 PEB 20570 PEB 20571 Functional Description Memory ADDR DMA Controller DREQR WR DACK + WR Data Bus Data DMA Mailbox 1-Cycle-Mode DELIC Figure 53 Single cycle DMA transfer mode for Receive Data Example for a single-cycle DMA transfer mode in receive direction (data is read from DELIC and written to memory) in Intel/Infineon Mode. Figure 53: 1. The DMA mailbox contains data (the receive mailbox contains up to 16 bytes of data) 2. DELIC requests DMA service via DREQR 3. DMA controller issuses a DMA Acknowledge (DACK) signal for addressing the DMA mailbox and a "read" signal for indicating DELIC that it will read the receive mailbox 4. In parallel, when the read data are stable on the bus, the DMA controller writes the data directly into the memory using ADDR and WR. Note: In Intel/Infineon Mode, WR is used as "read" signal for the receive mailbox. An example for a single-cycle DMA transfer in Intel/Infineon mode in transmit direction (data is read from memory and written into DELIC) is shown in Figure 54: Data Sheet 135 2003-07-31 PEB 20570 PEB 20571 Functional Description Memory ADDR DMA Controller DREQT RD DACK + RD Data Bus Data DMA Mailbox 1-Cycle-Mode-T DELIC Figure 54 Single cycle DMA transfer mode for Transmit Data 1. The DMA transmit mailbox is empty 2. DELIC requests DMA service via DREQT 3. The DMA controller addresses memory with ADDR and the DELIC with DACK 4. With read signal (RD), memory data reach the data bus 5. In parallel, when the data are stable on the bus, the DMA controller writes it directly into the transmit mailbox. Note: In Intel/Infineon Mode, RD is used as write signal for the transmit mailbox. 4.10.1 DMA Handshake In transactions between DMA controller and DELIC, the DELIC indicates that it is ready to transmit/ receive data by setting DREQT / DREQR high. The DMA controller answers by driving DACK low. DACK acts like a CS and remains low during the entire transaction. By driving DACK high, the DMA controller can stop the transaction on any stage, even if the data transfer has not been finished yet. DELIC Programming 1. Set the DMA transfer mode in MCFG register by the P to Memory-to-Memory or Flyby mode. Data Sheet 136 2003-07-31 PEB 20570 PEB 20571 Functional Description 2. Select the type of used data bus via DELIC pin "MODE": Intel/ Infineon or Motorola 3. Set byte count by writing the number of bytes to be transferred, minus 1, into DTXCNT/DRXCNT register (is handled by the OAK firmware). 4. Et the end of a transaction, OAK INT0 is automatically activated (if not masked) in order to indicate that the mailbox is empty and available for a next operation. The OAK can mask INT0 as a whole or just one of its components (for receive or transmit direction) via register DINSTA. 4.10.1.1 Two-cycle DMA Transfer Mode Depending on the selected bus mode (Intel / Infineon or Motorola), different signals are used. In Intel/Infineon mode, the control lines are DACK, RD, WR. Driving RD low when DACK is low causes a read from the mailbox. Driving WR low when DACK is low causes a write into the mailbox. In Motorola mode, the control lines are DACK, R/W, DS. Driving R/W high when DACK and DS are low causes a read from the mailbox. Driving R/W low when DACK and DS are low causes a write into the mailbox. 4.10.1.2 Fly-by Mode In Fly-by mode, the DMA transfer is done in one bus transaction. The DMA controller controls the DMA mailbox and the conventional memory within the same cycle; write strobe just when the read data is valid on the bus. See timing diagrams for Intel/Infineon and for Motorola bus type in Chapter 8. 4.10.2 PEC Mode. The PEC-mode supports Infineon Ps C16x, which use an integrated Peripherals Event Controller (PEC) as a DMA controller. This DMA controller is edge sensitive, meaning edges have to be provided on the DREQ line in order to initiate every DMA transfer. DREQ is internally controlled by the Read/Write signals. WR falling edge disables DREQT, i.e. drives it inactive, and RD falling edge does the same for DREQT. Rising edges of these signals enable DREQs again. 4.10.3 Transmit DMA Mailbox The Transmit DMA mailbox includes: * A 16-byte FIFO which the DMA controller writes in (addresses TDT0-7) and the OAK reads out as from 8 regular 16-bit-wide registers. * A 4-bit counter for indicating the number of transfers remaining in the current transaction (register DTXCNT). Data Sheet 137 2003-07-31 PEB 20570 PEB 20571 Functional Description * A 4-bit Interrupt status register (DINSTA), which actually belongs to both directions Transmit and Receive. The DELIC initiates all transfers, i.e. each transmit is initiated by the OAK. But the transfers are carried out by the DMA controller. If the DELIC transmits data e.g. to the GHDLC unit, the OAK writes the requested number of bytes (minus 1) into the DTXCNT register which causes the assertion of DREQT ("DMA Request for Transmit direction") pin. The DMA controller grants the bus to the DELIC, it drives DACK low and begins toggling the control lines. In Intel / Infineon (Memory-to-Memory) mode it drives WR line low when writing a byte to the mailbox. RD line stays high during all the "Write" transfer. DACK functions as a CS and is driven low during each "Write" access. Refer to AC specification, in Chapter 8. OAK INT0 DSP-tasks WR DTXCNT ISR: WR DTXCNT DREQT DACK WR 1 2 16 Figure 55 Timing in two-cycle DMA Mode for Transmit Direction and Infineon/ Intel Bus Type In Motorola (Memory-to-Memory) mode the DMA controller drives R/W line low during `Write' operations when DACK is low and DS is used for access timing. In Fly-by mode the meaning of `Read' and `Write' commands is opposite for the mailbox (see Chapter 4.10.1.2). After every `Write' operation the counter (DTXCNT) is decremented by one. DMA-operation is finished with the count down from 0H to the value 'FH'. The DMA controller can stop the transaction (before frame end) driving DACK high. The DELIC continues keeps DREQT active, stops decrementing DTXCNT and waits until DACK becomes low again. Data Sheet 138 2003-07-31 PEB 20570 PEB 20571 Functional Description After the DMA Controller has written the requested number of bytes to the transmit mailbox, DTXCNT becomes 'FH', and DREQT is deasserted. Register DINSTA can be programmed to cause an interrupt (INT0) to the OAK. The OAK can now read the data from the transmit mailbox: - 1st byte in least significant (LS) byte of LS word of the FIFO - 2nd byte in most significant (MS) byte of LS word of the FIFO, and so on Note: 1. In case of an odd number of bytes, the last byte is available as the LS byte of the last word while the MS byte of this word is do not care. 2. The OAK reads data word-by-word, exactly like in a non-DMA transfer. Data Transfer via the Transmit Mailbox - Steps 1. The OAK writes into DTXCNT the number of bytes to be transferred minus one (Tr_Num). 2. DREQT is asserted ("high" or "low" depending on register MCFG:DRQLV). 3. The DMA asserts DACK = 0 and issues (Tr_Num+1) write transactions to the mailbox ("FIFO"). 4. DREQT is deasserted ("low" or "high"). 5. If bit DINSTA:TMSK is inactive ("1"), the DMA interrupt (INT0) of the OAK is activated. 6. The OAK reads Tr_Num bytes from the mailbox. Note: The OAK must not write to the register DTXCNT while the previous DMA transfer has not been finished. (The OAK waits for Transmit DMA Interrupt and tests if DTXCNT equals 'FH'.) 4.10.4 Receive DMA Mailbox The receive mailbox includes: * A 16-byte FIFO which the OAK writes into as in 8 regular 16-bit-wide registers and the DMA controller reads out like from a FIFO (RDT0-7). * A 4-bit counter for indicating the number of transactions that remain for the transfer (DRXCNT). The DELIC initiates all transfers, i.e. each receive is initiated by the OAK. But the transfers are done by the DMA controller. When the DELIC receives data e.g. from the GHDLC Unit, the OAK writes this data into the receive mailbox whereas the 1st byte is put into LS byte of LS word, the 2nd byte into MS byte of LS word, and so on. Note: In case of an odd number of bytes, the MS byte of the last word is don't care. Then the OAK writes the byte count into register DRXCNT, which causes the assertion of DREQR ("DMA Request for Receive direction") pin. Data Sheet 139 2003-07-31 PEB 20570 PEB 20571 Functional Description If the DMA controller grants the bus to the DELIC, it drives DACK low and begins toggling the control lines. In Memory-to-Memory mode on Intel / Infineon bus type, it drives RD line low when reading from the receive mailbox. The WR line stays high during all the "Read" transfer. DACK functions as a CS and is driven low during each "Read" access. In Memory-to-Memory mode on Motorola bus type, the DMAC drives R/W line 'high' during `Read' operations while DACK is low and DS controls the read access. In Fly-by mode the meaning of `Read' and `Write' commands is opposite for the mailbox (see Chapter 4.10.1.2). After each `Read' operation the counter (DRXCNT) is decremented by one. DMA-operation finishes with the count down from 0H to the value 'FH'. The DMA controller can stop the transaction (before frame end) driving DACK high. The DELIC continues driving DREQR active, stops decrementing DRXCNT and waits until DACK becomes low again. After the DMA controller has read the requested number of bytes from the receive mailbox, DRXCNT becomes 'FH', and DREQR is deasserted. DINSTA can be programmed to cause an interrupt (INT0) to the OAK. OAK INT0 DSP-tasks WR DRXCNT ISR INT0: WR DRXCNT DREQR DACK RD 1 2 16 Figure 56 Timing in two-cycle DMA Mode for Receive Direction and Infineon/ Intel Bus Type Receive Data via the Receive Mailbox-Steps 1. The OAK writes the received data to into the receive mailbox. 2. The OAK writes the number of bytes to be transferred minus one into DRXCNT (Rc_Num). 3. DREQR is asserted ("high" or "low"). Data Sheet 140 2003-07-31 PEB 20570 PEB 20571 Functional Description 4. The DMA controller asserts DACK and issues (Rc_Num+1) read transactions from the receive mailbox ("FIFO"). 5. DREQR is deasserted ("high" or "low"). 6. If RMSK bit in DINSTA is inactive ("1"), the DMA interrupt to OAK (INT0) is activated. Note: The OAK must not write to the register DRXCNT while the previous DMA receive transaction has not been finished. (The OAK waits for Receive DMA Interrupt and tests if DTXCNT equals 'FH'.) 4.10.5 FIFO Access The FIFO size is 16 bytes (8 words) each (Transmit, Receive). On the OAK side, each of the 8 data registers (TDT0-7 and RDT0-7) can be accessed separately. On the DMA controller side, only the current top of FIFO is accessible. Note: The Transmit FIFO and the Receive FIFO are functioning as explained above only when the mailbox is in DMA mode (MCFG:DMA = `1'). In case of non-DMA mode (MCFG:DMA = `0') the FIFOs are used as secondary (extension) to the general mailbox, which means that the general mailbox will have 16 words for each direction (OAK and P), instead of 8. Data Sheet 141 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.11 4.11.1 Clock Generator Overview The DELIC clock generator provides all necessary clock signals for the DELIC and connected clock slave devices. The internal clocks are generated by two on-chip PLLs: 1. A digital controlled oscillator (DCXO) generates a 16.384 MHz clock from an external crystal. 2. A PLL multiplies the 16.384 MHz clock to a 61.44 MHz clock. An overview of the clock signals and a block diagram is shown below. Table 43 Pin CLK16-XI XCLK REFCLK PFS PDC Overview of Clock Signals Function 16.384 MHz External Crystal Input External Reference Clock from layer-1 IC (2.048 MHz, 1.536 MHz or 8 kHz) PCM Reference Clock (8 kHz or 512 kHz) I/O During Reset I O I I O I (1.536 MHz) CLK16-XO 16.384 MHz External Crystal Output I/O tristate PCM Frame Synchronization 8 kHz (I/O) or 4 kHz (I) I/O I (Slave) O (Master) PCM Data Clock (2.048, 4.096, 8.192 or 16.384 MHz) I/O I (Slave) O (Master) (2.048 MHz) Auxiliary Clock (2.048, 4.096, 8.192, 16.384, or 15.36 MHz) O O O O (4.096 MHz) O (3.072 MHz) O (384 kHz) O O (7.68 MHz) I CLKOUT DCL_2000 IOM-2000 Data Clock (3.072, 6.144 or 12.288 MHz) DCL FSC L1_CLK DSP_CLK IOM-2 Data Clock (384 kHz, 768 kHz, 2.048 MHz or 4.096 MHz) Layer-1 Clock 15.36 or 7.68 MHz (e.g. OCTAT-P / QUAT-S) IOM-2 and IOM-2000 Frame Synchronization 8 kHz. O O DSP Test Clock. I (to run the DSP at clock rates other than 61.44 MHz) Data Sheet 142 2003-07-31 PEB 20570 PEB 20571 Functional Description XCLK REFCLK (reference clock from (reference clock L1 device, PCM) 1.536 MHz or 512 kHz / 8 kHz 2.048 MHz or 8 KHz) 16.384 MHz CLK16-XI CLK16-XO Filter DELIC SHP DCXO PD REFS :1 :3 :4 :192 :256 :192 :256 :1 8 KHz 16.384 MHz 3.072 MHz 6.144 MHz 12.288 MHz DCL_2000 DSP_CLK (Fallback) PLL 61.44 :20 MHz :64 :1 :10 :5 8 KHz MUX DSP CLK 8 KHz 8 kHz MUX 8 KHz PFS M/S(strap option) PDC 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz CLKOUT LCLK MUX GHDLC :2 :8 :1 :2 :2 15.36 MHz 7.68 MHz L1_CLK 384 kHz 768 kHz 1.536 MHz 2.048 MHz 4.096 MHz DCL 8 kHz FSC :15 :2 :30 :80 :160 :256 2.048 MHz :2 4.096 MHz M/S MUX :2 8.192 MHz :2 :48 :96 :2 :256 :512 16.384 MHz 15.36 MHz Short FSC Figure 57 DELIC Clock Generator Data Sheet 143 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.11.2 DSP Clock Selection The default DSP clock is the internal 61.44 MHz generated by the PLL. For test purpose, a different frequency may be provided via DSP_CLK input pin. The selection between the internal 61.44 MHz or external clock source is done by the DSP_FRQ input pin. 4.11.3 PCM Master/Slave Mode Clocks Selection In PCM Master mode, the PFS and PDC are derived from the internal 16.384 MHz signal, and driven to the PCM interface via the PFS pin (output) and PDC pin (output). In PCM Slave mode, the PFS and PDC are generated from an external signal, and input to the DELIC via the PFS pin and the PDC pin. Note: During reset, a strap pin determines whether the DELIC operates in clock Master or Slave mode. When setting to slave mode the register PFS SYNC (Chapter 6.2.11.10) has to be written in order to align the clocks. 4.11.4 DELIC Clock System Synchronization The PCM clock division chain is synchronized to an external reference clock, used as one of the inputs to a phase comparator, after being divided into 8 KHz. The other phase comparator input is the 8 KHz clock, derived from the 16.384 MHz clock. The phase comparator output is used as control input of the DCXO, after being filtered by a low-pass filter. The reference clock can be driven by one of the following input pins: * XCLK - 2.048 MHz, 1.536 MHz or 8 KHz: Can be driven by a layer-1 transceiver (e.g. VIP, QUAT-S) connected to the Central Office. Only a clock master DELIC can be synchronized directly according to this input. In other cases (clock slave DELIC), this input signal may be divided to 8 KHz or 512 KHz, and driven out via REFCLK, in purpose to be used for the synchronization of the clock-master DELIC. * REFCLK - 512 KHz or 8 KHz: Used for synchronization of the clock master DELIC, when not synchronized by XCLK. Usually this signal is driven by a clock slave DELIC, or another PBX in the system. In a clock slave DELIC this pin is used as output. * PFS - 8 KHz: Driven by the system clock master. May be used for synchronization of the clock slave DELICs. In a clock master DELIC this pin is used as output. 4.11.5 IOM-2 Clock Selection The IOM-2 interface clocks FSC and DCL are always output. The FSC output signal is usually generated with 50% duty cycle. A short FSC pulse is required for multiframe start indication (one DCL cycle long). One cycle after the short FSC pulse, the normal FSC is generated again with 50% duty cycle. Data Sheet 144 2003-07-31 PEB 20570 PEB 20571 Functional Description 4.11.6 IOM-2000 Clock Selection The IOM-2000 interface uses the same FSC like IOM-2, whereas the data clock DCL2000 is a dedicated pin (always output). 4.11.7 REFCLK Configuration REFCLK is an I/O pin for synchronizing the PCM interface (to 8 kHz or 512 kHz). The clock master DELIC may synchronize the internal clocks to REFCLK by selecting REFCLK as the reference clock source. A clock slave DELIC may use REFCLK as output, when REFCLK is driven by the XCLK input pin. The slave DELIC may transfer the XCLK signal to the clock master DELIC, and enable the clock master to synchronize to a layer-1 device, which is connected to another DELIC in the system. 4.11.8 GHDLC Clock Selection Any of the next signals may be provided to the GHDLC channel as input clock: 1. LCLK Input Pin This option is possible only when a LNC interface is assigned to the GHDLC unit. 2. 2.048 MHz, 4.096 MHz, 8.192 MHz or 16.384 MHz These clock signals are generated internally by the PCM clocking path. The selected internal clock is also driven outward via LCLK. Note: One of these signals must be selected as the clock of the GHDLC channel when the DELIC is the clock master of this channel. Note: It's not possible to operate a GHDLC-channel with 16.384 MHz. However if the respective port isn't used this clock can be driven externally. Data Sheet 145 2003-07-31 PEB 20570 PEB 20571 DELIC Memory Structure 5 DELIC Memory Structure The following tables provide the DELIC memory map for the DSP and the P. 5.1 5.1.1 T DSP Address Space DSP Register Address Space DSP Registers Address Space Description DCU registers A/-law registers IOMU registers PCMU registers Clocks registers TRANSIU registers GHDLC registers P Mailbox and DMA Mailbox registers HDLCU registers not used Table 44 Address D000 - D01F D020 - D03F D040 - D05F D060 - D07F D080 - D09F D0A0 - D0BF D0C0 - D0DF D100 - D17F D180 - D1FF D1A0 - DFFF 5.1.2 Table 45 Address DSP Program Address Space DSP Program Address Space Size 4Kw 58Kw 2Kw Description Program RAM Not used Program ROM 0000 - 0FFF 1000 - F7FF F800 - FFFF Data Sheet 146 2003-07-31 PEB 20570 PEB 20571 DELIC Memory Structure 5.1.3 A1 DSP Data Address Space Occupied DSP Data Address Space Size 1Kw 64w 64w 32w 32w 32w 32w 32w 32w 96w 96w 192w 72w 72w 64w 64w 128w 24w 24w 128w 128w 256w 4Kw 0.5Kw 1Kw-16w 16w 1Kw Description Internal XRAM GHDLC data buffer reserved for test (**) HDLCU receive output buffer HDLCU transmit input buffer HDLCU command RAM HDLCU receive input buffer HDLCU transmit output buffer HDLCU status buffer TRANSIU receive data buffer TRANSIU transmit data buffer reserved for test (**) reserved for test (**) reserved for test (**) IOMU receive data buffer IOMU transmit data buffer reserved for test (**) HRAM for U PN scrambler HRAM for U PN descrambler PCMU receive data buffer PCMU transmit data buffer reserved for test (**) OAK memory mapped registers(*) A/-Law ROM Emulation mail box (on SCDI) OCEM(R) Registers Internal YRAM Table 46 Address 0000 - 03FF 2000 - 203F 2040 - 207F 4000 - 401F 4020 - 403F 4040 - 405F 4060 - 407F 4080 - 409F 40A0 - 40BF 6000 - 605F 6080 - 60DF 6100 - 61BF 6200 - 6248 6280 - 62C8 8000 - 803F 8040 - 807F 8080 - 80FF 9000 - 9017 9020 - 9037 A000 - A07F A080 - A0FF A100 - A1FF D000 - DFFF E000 - E1FF F400 - F7EE F7F0 - F7FF FC00 - FFFF Data Sheet 147 2003-07-31 PEB 20570 PEB 20571 DELIC Memory Structure Note: (*) The OAK memory mapped registers address space is described in the following table: (**) Accessing these addresses may cause unpredictable results. Table 47 Address D000 - D01F D020 - D03F D040 - D05F D060 - D07F D080 - D09F D0A0 - D0BF D0C0 - D0DF D100 - D17F D180 - D1FF D1A0 - DFFF OAK Memory Mapped Registers Address Space Description DCU registers A/m-law registers IOMU registers PCMU registers Clocks registers TRANSIU registers HDLCU registers CPU+DMA mailbox registers GHDLC registers not used For connecting a HDLC channel to a subscriber, the receive and transmit time slot address must be determined. Usually the HDLC channels perform signalling to a terminal which can be accessed via IOM2 or IOM2000 interface. Either D-channel handling (2 bit) or signalling via a B-channel (8 bit) can be selected. The following figures show the memory organization and help to determine initialization addresses for the HDLC software registers. The TRANSIU receive and transmit buffers are accessed directly by the DSP: switchingand HDLC-tasks. Accesses to the 'Operation Mode Command and Status Bits' are possible via addresses: 6003H + n * 4 with n = 0..23. Data Sheet 148 2003-07-31 PEB 20570 PEB 20571 DELIC Memory Structure TRANSIU Receive Buffer 6000H 6001H 6002H 6003H 6004H 6005H 6006H 6007H B1-channel data B2-channel data D B1-channel data B2-channel data D VIP0 Channel 0 VIP0 Channel 1 ... 605CH 605DH 605EH 605FH B1-channel data B2-channel data D VIP2 Channel 7 6080H 6081H 6082H 6083H 6084H 6085H 6086H 6087H B1-channel data B2-channel data D B1-channel data B2-channel data D VIP0 Channel 0 VIP0 Channel 1 TRANSIU Transmit Buffer ... 60DCH 60DDH 60DEH 60DFH B1-channel data B2-channel data D VIP2 Channel 7 Figure 58 TRANSIU Buffer Addresses Data Sheet 149 2003-07-31 PEB 20570 PEB 20571 DELIC Memory Structure 5.2 P Address Space The P address space consists of the general mail-box registers, the DMA mail-box registers (only in non-DMA mode), the P-interface control register, and the P-interface status register (MISR) . Table 48 Address 00H - 43H 60H - 62H 48H, 68H, 6AH 6BH - 7FH P Address Space Table Description P- mail box registers P-configuration registers Reserved. Accessing these addresses may cause unpredictable results Data Sheet 150 2003-07-31 PEB 20570 PEB 20571 Register Description 6 6.1 Table 49 Reg Name TICR TCCR0 TCCR1 TCCR2 VIPCMR0 VIPCMR1 VIPCMR2 VIPSTR0 VIPSTR1 VIPSTR2 TICCMR Register Description Register Map TRANSIU Register Map Access Address RD/WR RD/WR RD/WR RD/WR WR WR WR RD RD RD WR D0A0H D0A1H D0A2H D0A3H D0A8H D0A9H D0AAH D0AC D0ADH D0AEH Reset Value 0000H FFFFH FFFFH FFFFH 0000H 0000H 0000H 0000H 0000H 0000H Comment IOM-2000 global configuration Channel 7..0 configuration Channel 15..8 configuration Channel 23..16 configuration VIP_0 command registers VIP_1 command registers VIP_2 command registers VIP_0 status register VIP_1 status register VIP_2 status register Channel initialization command Page No. 161 162 162 162 164 164 164 167 167 167 168 D0B0H 0000H (LS-word) D0B1H 0000H (MS-word) 0000H D0B2H (LS-word) D0B3H 0000H (MS-word) 0000H D0B4H (LS-word) D0B5H 0000H (MS-word) TICSTR RD Channel initialization status 173 TUTLR RD/WR Up test loop register 174 Data Sheet 151 2003-07-31 PEB 20570 PEB 20571 Register Description Table 50 Reg Name SCMOD SCSTA Table 51 Reg Name ICR ISR ITSCR Scrambler Register Map Access Address RD/WR RD/WR D010H D011H Reset Value 0003H undef. Comment Scrambler mode Scrambler status Page No. 175 176 IOMU Register Map Access Address R/W R Set (W) Reset (W) R D040H D041H D042H D043H D044H D045H D046H undef. IOMU DRDY 181 182 00E0H IOMU Data Prefix Reset Value 0002H undef. 0000H Comment IOMU Control IOMU Status IOMU Tri-State Control Page No. 177 178 179 IDRDYR IDPR R R/W Table 52 Reg Name PCR PSR PTSC0 PCMU Register Map Access Address RD/WR RD RD/WR D060H D061H Reset Value 00H undef. Comment PCMU Control PCMU Status PCMU Tristate control 0 Page No. 183 184 185 00H D062H (read/set) D063H (read/reset) 00H D064H (read/set) D065H (read/reset) 00H D066H (read/set) D067H (read/reset) PTSC1 RD/WR PCMU Tristate control 1 185 PTSC2 RD/WR PCMU Tristate control 2 185 Data Sheet 152 2003-07-31 PEB 20570 PEB 20571 Register Description Table 52 Reg Name PTSC3 PCMU Register Map (cont'd) Access Address RD/WR Reset Value Comment PCMU Tristate control 3 Page No. 185 00H D068H (read/set) D069H (read/reset) 00H D06AH (read/set) D06BH (read/reset) 00H D06CH (read/set) D06DH (read/reset) 00H D06EH (read/set) D06FH (read/reset) 00H D070H (read/set) D071H (read/reset) D072H E0H PTSC4 RD/WR PCMU Tristate control 4 185 PTSC5 RD/WR PCMU Tristate control 5 185 PTSC6 RD/WR PCMU Tristate control 6 185 PTSC7 RD/WR PCMU Tristate control 7 185 PDPR . RD/WR PCMU Data Prefix 187 Table 53 Reg Name AMCR AMIR AMOR A-/-Law Unit Register Map Access Address R/W W R D020H D021H D022H Reset Value 00H Comment A/-law Unit Control Page No. 188 189 190 undefin A/-law Unit Input ed undefin A/-law Output ed Data Sheet 153 2003-07-31 PEB 20570 PEB 20571 Register Description Table 54 Reg Name HCR HSTA HCCV HCSV HDLCU Register Map Access Address W R R/W R D180H D180H 4040H-405FH Reset Value 0001H 0001H Comment HDLC Control HDLC Status Page No. 191 192 193 195 undefin Channel Command Vector ed 40A0H-40BFH undefin Channel Status Vector ed Table 55 Reg Name GTEST GCHM GINT GFINT GRSTA0 GRSTA1 GRSTA2 GRSTA3 RXDAT GMOD0 GMOD1 GMOD2 GMOD3 GTCMD0 GTCMD1 GTCMD2 GTCMD3 GASYNC GLCLK0 Data Sheet GHDLC Register Map Access Address W W R R/W R R R R RD W W W W W W W W R/W R/W D0C0H D0C1H D0D4H D0D3H D0C2H D0C3H D0C4H D0C5H 2000H203FH D0C6H D0C7H D0C8H D0C9H D0CAH D0CCH D0CEH D0D0H D0D2H D08AH Reset Value 0001H 0000H 0000H 0000H 001FH 001FH 001FH 001FH 0000H 0140H 0140H 0140H 0140H 0000H 0000H 0000H 0000H 0000H 0000H 154 Comment GHDLC Test/ Normal Mode GHDLC Channel Mode GHDLC Interrupt GHDLC Frame Interrupt GHDLC Receive Status cha. 0 GHDLC Receive Status cha. 1 GHDLC Receive Status cha. 2 GHDLC Receive Status cha. 3 Receive data and status GHDLC Mode cha. 0 GHDLC Mode cha. 1 GHDLC Mode cha. 2 GHDLC Mode cha. 3 GHDLC TX Command cha. 0 GHDLC TX Command cha. 1 GHDLC TX Command cha. 2 GHDLC TX Command cha. 3 ASYNC Control/ Status LCLK0 Control Register Page No. 197 198 199 200 201 201 201 201 203 204 204 204 204 206 206 206 206 207 208 2003-07-31 PEB 20570 PEB 20571 Register Description Table 55 Reg Name GLCLK1 GLCLK2 GLCLK3 MUXCTRL ST2 GHDLC Register Map (cont'd) Access Address R/W R/W R/W R/W W D08BH D08CH D08DH D14AH OAK register Reset Value 0000H 0000H 0000H 0000H xxxx xx0x xxxx xxxxB Comment LCLK1 Control Register LCLK2 Control Register LCLK3 Control Register Multiplexer Control GHDLCU frame frequency Page No. 209 210 211 212 213 Table 56 Reg Name IMASK STEVE STATC STATI DCU Register Map Access R/W R R R Address D002H D003H D004H D005H Reset Value 0000H 0000H 0000H Comment Interrupt Mask Status Event Statistics Page No. 214 215 216 217 unchan. Statistics Counter Table 57 Reg. P Configuration Register Map PP Bit DSP Addr. Byte Word Access Access MSB of Word 6 8 R R/W R/W R none none PAddr. LSB of Word 48H 68H DSP Addr. Page No. (16 bit) DesReset cription Value MCFG configur 0H ation IVEC int vector reg unchanged D148H D168H 218 220 Data Sheet 155 2003-07-31 PEB 20570 PEB 20571 Register Description Table 58 Register (16 bit) General Mailbox Register Map Description Reset Value Bit DSP P PWord Byte Addr. Access Acc. MSB of Word 8 1 R W W R W none 41H 43H PDSP Addr. Addr. LSB of Word 40H none 42H Pag e No. MCMD P command MBUS Y MGEN 00H D140H 221 D141H 222 D142H 223 (LSB) D143H (MSB) D144H (All) D100H 224 D102H 224 D104H 224 D106H 224 D108H 224 D10AH 224 D10CH 224 D10EH 224 D160H 225 D161H 226 P MB busy 0H P generic data reg. unchanged 16 R MDT0 MDT1 MDT2 MDT3 MDT4 MDT5 MDT6 MDT7 OCMD OBUS Y P data reg0 P data reg1 P data reg2 P data reg3 P data reg4 P data reg5 P data reg6 P data reg7 DSP command DSP MB busy unchanged 16 R unchanged 16 R unchanged 16 R unchanged 16 R unchanged 16 R unchanged 16 R unchanged 16 R unchanged 16 R 00H 0H 8 1 W R W W W W W W W W R 01H 03H 05H 07H 09H 0BH 0DH 0FH none 00H 02H 04H 06H 08H 0AH 0CH 0EH 60H none R/W 61H Data Sheet 156 2003-07-31 PEB 20570 PEB 20571 Register Description Table 58 Register (16 bit) General Mailbox Register Map (cont'd) Description Reset Value Bit DSP P PByte Addr. Word Access Acc. MSB of Word R 63H DSP PAddr. Addr. LSB of Word 62H Pag e No. OGEN DSP generic data reg unchanged 16 W D162H 227 (LSB) D163H (MSB) D164H (All) D120H 228 D122H 228 D124H 228 D126H 228 D128H 228 D12AH 228 D12CH 228 D12EH 228 ODT0 ODT1 ODT2 ODT3 ODT4 ODT5 ODT6 ODT7 DSP data reg0 DSP data reg1 DSP data reg2 DSP data reg3 DSP data reg4 DSP data reg5 DSP data reg6 DSP data reg7 unchanged 16 W unchanged 16 W unchanged 16 W unchanged 16 W unchanged 16 W unchanged 16 W unchanged 16 W unchanged 16 W R R R R R R R R 21H 23H 25H 27H 29H 2BH 2DH 2FH 20H 22H 24H 26H 28H 2AH 2CH 2EH Note: MDT8..15 and ODT8..15 are accessible only in non-DMA mode, when the DMA Mailbox data registers are used for doubling the size of General Mailbox. Data Sheet 157 2003-07-31 PEB 20570 PEB 20571 Register Description Table 59 Register DMA Mailbox Register Map Description Reset Value 0H 0H unchange d unchange d Bit DSP Acces s 4 4 R/W R DMA P P DSP Page / P MSB LSB Addr. No. Acc. Addr. Addr. none none none none W 11H none none 10H D150 H DTXCN T Tx counter 229 231 224 DINSTA DMA Int status TDT0/ MDT8 TDT1/ MDT9 TDT2/ MDT10 TDT3/ MDT11 TDT4/ MDT12 TDT5/ MDT13 TDT6/ MDT14 TDT7/ MDT15 Tx data reg0/ P data reg8 Tx data reg1/ P data reg9 D152 H 16 R D110 H 16 R W 13H 12H D112 H 224 Tx data reg2/ unP data reg10 change d Tx data reg3/ unP data reg11 change d Tx data reg4/ unP data reg12 change d Tx data reg5/ unP data reg13 change d Tx data reg6/ unP data reg14 change d Tx data reg7/ unP data reg15 change d 0H unchange d 16 R W 15H 14H D114 H 224 16 R W 17H 16H D116 H 224 16 R W 19H 18H D118 H 224 16 R W 1BH 1AH D11A 224 H 16 R W 1DH 1CH D11C 224 H 16 R W 1FH 1EH D11E 224 H DRXCN Rx counter T RDT0/ ODT8 Rx data reg0/ DSP data reg8 4 R/W none none R 31H none 30H D170 H 230 228 16 W D130 H Data Sheet 158 2003-07-31 PEB 20570 PEB 20571 Register Description Table 59 Register DMA Mailbox Register Map (cont'd) Description Reset Value unchange d unchange d unchange d unchange d unchange d unchange d unchange d Bit DSP Acces s 16 W DMA P P DSP Page / P MSB LSB Addr. No. Acc. Addr. Addr. R 33H 32H D132 H RDT1/ ODT9 RDT2/ ODT10 RDT3/ ODT11 RDT4/ ODT12 RDT5/ ODT13 RDT6/ ODT14 RDT7/ ODT15 Rx data reg1/ DSP data reg9 Rx data reg2/ DSP data reg10 Rx data reg3/ DSP data reg11 Rx data reg4/ DSP data reg12 Rx data reg5/ DSP data reg13 Rx data reg6/ DSP data reg14 Rx data reg7/ DSP data reg15 228 16 W R 35H 34H D134 H 228 16 W R 37H 36H D136 H 228 16 W R 39H 38H D138 H 228 16 W R 3BH 3AH D13A 228 H 16 W R 3DH 3CH D13C 228 H 16 W R 3FH 3EH D13E 228 H Note: MDT8..15 and ODT8..15 are accessible only in non-DMA mode, when the DMA Mailbox data registers are used for doubling the size of General Mailbox. .. Data Sheet 159 2003-07-31 PEB 20570 PEB 20571 Register Description Table 60 Reg Name CPDC CPFS CLKOUT CREFSEL CREFCLK CDCL2 CDCL CFSC CL1CLK CPFSSY CRTCNT CSTRAP Clock Generator Register Map Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Address D080H D081H D082H D083H D084H D085H D086H D087H D088H D089H D08EH D08FH Reset Value 0000H 0001H 0008H 0000H 0003H 0004H 000BH 0002H 0000H 0000H 0000H xxxx xxxx xxxx xx10B Comment PDC Control PFS Control CLKOUT Control DCXO Reference Clock Selection REFCLK Control DCL_2000 Control DCL Control FSC Control L1_CLK Control PFS Synchronization Mode Real-time Counter Strap Status Register Page No. 232 233 234 235 236 236 238 239 240 241 242 243 Data Sheet 160 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2 6.2.1 6.2.1.1 Detailed Register Description TRANSIU Register Description TRANSIU IOM-2000 Configuration Register read/write Address: D0A0H TICR Register Reset value: 0000H Note: The reset value of bit 4KFSC is undefined, since this read-only bit is toggled every 250 s. 15 x 7 x DR1..0 14 x 6 x 13 x 5 x 12 x 4 4KFSC 11 x 3 CMDEN 10 x 2 DXEN 9 x 1 DR1 8 x 0 DR0 IOM-2000 Data Rate and Channel Number 00 = 01 = 10 = 11 = 3.072 Mbit/s data rate; 8 IOM-2000 channels are supported 6.144 Mbit/s data rate; 16 IOM-2000 channels are supported 12.288 Mbit/s data rate; 24 IOM-2000 channels are supported Reserved IOM-2000 DX line to the VIP is in tri-state IOM-2000 DX line to the VIP is enabled (starting with the next 4 kHz frame) IOM-2000 CMD line to the VIP is in tri-state IOM-2000 CMD line to the VIP is enabled (starting with the next 4 kHz frame) In the TRANSIU, the current 8 kHz IOM-2000 frame starts in the second half of the current 4 kHz UPN of S/T frame In the TRANSIU, the current 8 kHz IOM-2000 frame starts in the first half of the current 4 kHz UPN of S/T frame DXEN DX Line Enable 0= 1= CMDEN CMD Line Enable 0= 1= 4KFSC 4 kHz FSC (read only) 0= 1= Note: 'x' = unused (read as '0') Data Sheet 161 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.1.2 TRANSIU Channel Configuration Registers The Channel registers are used for IOM-2000 channel disabling and mode programming. Each IOM-2000 channel may be programmed to UPN, LT-S, or LT-T mode, or completely disabled. Important Only four channels out of eight channels are programmable to UPN and S/T modes in VIP PEB 20590, the remaining four channels may be operated as UPN transceiver only. It is the user's responsibility to ensure that the IOM-2000 channels in the TRANSIU are correctly configured in order to match with the line configuration of the VIP see below: Table 61 VIP_0,1,2 channel TRANSIU channel Available VIP Mode Available VIP8 Mode Available ISDN Modes for Each VIP Channel 0 0 8 16 UPN UPN S/T 1 1 9 17 UPN S/T UPN S/T 2 2 10 18 UPN UPN S/T 3 3 11 19 UPN S/T UPN S/T read/write 4 4 12 20 UPN UPN S/T 5 5 13 21 UPN S/T UPN S/T 6 6 14 22 UPN UPN S/T 7 7 15 23 UPN S/T UPN S/T Registers TCCR0 - 2 Address: TCCR0: D0A1H TCCR1: D0A2H TCCR2: D0A3H Reset values: FFFFH 15 14 13 12 11 10 9 8 C7M(1:0) 7 6 C6M(1:0) 5 4 C5M(1:0) 3 2 C4M(1:0) 1 0 C3M(1:0) C2M(1:0) C1M(1:0) C0M(1:0) Data Sheet 162 2003-07-31 PEB 20570 PEB 20571 Register Description C7..0M(1:0) Operational Mode of IOM-2000 Channel7..0 00 = 01 = 10 = 11 = Channel is configured to S mode (LT-S) Channel is configured to S mode (LT-T) Channel is configured to UPN mode Channel is disabled, '0's are sent on the DX line Note: TCCR0 (channel 7..0), TCCR1 (channel 15..8) and TCCR2 (channel 23..16) have the same structure, only TCRR1 is shown here. Note: IOM-2000 cha. 0 and 1 are restricted to the modes LT-S and UPN. This means that TCCR0:C0M1..0 and TCCR0:C1M1..0 must not be programmed to the value 01. Data Sheet 163 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.1.3 VIP Command Registers (VIPCMR0, VIPCMR1, VIPCMR2) The VIPCMR0-2 registers contain command information dedicated to the VIP 0, 1, 2 (only the VIPCMR0 is shown here, VIPCMR1 and VIPCMR2 have the same structure). VIPCMR Register write Address: VIPCMR0: D0A8H VIPCMR1: D0A9H VIPCMR2H: D0AAH Reset value: 0000H 15 x 7 14 x 6 DELCH(2:0) 13 x 5 12 x 4 EXREF 11 RD_n 3 10 9 8 PLLPPS SH_FSC DELRE 2 REFSEL (2:0) 1 0 WR_n WR_n Write Command to VIP_n (S/T, UPN) 0= 1= Data sent to VIP_n is invalid Data sent to VIP_n is valid REFSEL(2:0) Reference Clock Channel Select (LT-T) The reference clock signal for the DELIC oscillator is generated from the internal VIP_n Channel_m coded in these 3 bits and passed on via pin REFCLK to the next cascaded VIP or directly to the DELIC 000 = 001 = ... 007 = Reference clock provided by Channel_7 Reference clock provided by Channel_0 Reference clock provided by Channel_1 EXREF External Reference Clock Selection (LT-T) Data Sheet 164 2003-07-31 PEB 20570 PEB 20571 Register Description 0= No external reference clock source. Reference clock is generated from internal VIP_n channel specified in REFCLK(2:0) and passed on via REFCLK pin to VIP_n-1 or directly to DELIC. Reference clock is generated from external source via pin INCLK and passed on via REFCLK pin to VIP_n-1 or directly to DELIC. The internal reference clock generation logic is disabled. Note that VIP_0 has the highest priority in terms of clock selection 1= DELCH(2:0) Delay Measurement Channel Selection (UPN) Selects one of the eight UPN line interface channels of each VIP where the delay is to be measured. 000 = 001 = ... 111 = Delay is measured in UPN Channel_7 Delay is measured in UPN Channel_0 Delay is measured in UPN Channel_1 DELRE Delay Counter Resolution (UPN) Resolution of the delay counter. 0= 1= Resolution of 65 ns (15.36 MHz period) Resolution of 130 ns (7.68 MHz period) Note: Using a resolution of 65 ns, the maximum delay of 20.8 s is not covered (refer to DELAY(7:0) bits) SH_FSC Short FSC Pulse 0= 1= The next FSC frame is no superframe The next FSC is assumed as superframe Normal operation The clock recovering PLLs of all VIP channels operate on positive line pulses only No register read PLLPPS PLL Positive Pulse Sensing 0= 1= RD_n Read Request to VIP Status Register S_n (S/T, UPN) 0= Data Sheet 165 2003-07-31 PEB 20570 PEB 20571 Register Description 1= The DSP reads the VIP register (during initialization, debugging or error conditions). The register value is available for the read operation in the consecutive frame (after the next FSC). Note: To avoid blocking, the DSP must not issue this bit during normal operation. Note: Unused bits (x) read as `0'. The registers are reset upon every 8 kHz frame sync to avoid multiple data transmit/receive to/from the VIP. Data Sheet 166 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.1.4 VIP Status Registers The VIPSTR0-2 registers contain the status bits received from the dedicated VIP for VIPs 0, 1, 2 respectively (all three registers have the same structure). VIPSTR Register VIPSTR0: D0ACH, read Address: VIPSTR1: D0ADH, VIPSTR2: D0AEH Reset value: 0000H 15 x 7 14 x 6 13 x 5 12 x 4 11 x 3 10 9 8 x 0 VIPVNR(1..0) 2 1 DELAY(7:0) DELAY(7:0) Line Delay Value (UPN) Returns the value of the measured line delay (in s) between the UPN transmit and receive frame with a resolution of 65 ns or 130 ns (programmable in VIPCMR.DELRE bits). The value indicates the delay between the transmitted M-bit and the received LF-bit (minus the UPN guard time of 2 bits). The delay for one direction equals to the measured delay divided by two. The channel address for the delay measurement is coded in VIPCMR.DELCH(2:0) bits. The VIP provides 2 values in one UPN frame (one every 125 s) from which the bigger one is the valid. Note: The transceiver delays of the VIP are included in the delay measurement. VIPVNR(1..0) VIP Version Number 0= 1= VIP version V1.1 VIP version V2.1 Note: Unused bits (x) read as `0'. Data Sheet 167 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.1.5 TRANSIU Initialization Channel Command Register The Initialization Channel Command Register contains the Command bits for VIP_n, Channel_m together with 5 bits of the VIP channel address. The VIP only acts upon the command bits if they were declared valid by the DELIC issuing a write command. Bit WR is dedicated to the command bits of groups CONF1, CONF2 and TST2, whereas WR_ST informs the VIP about changes in the layer 1 state machine of the DELIC (SMINI(2:0) and MSYNC bits). The DELIC may also explicitly read the VIP's status information by issuing bit RD. The reset value of each bit is '0' except bits MODE(2:0) which are set to '011' Note: A read command to the VIP must not be issued during normal operation to avoid a loss of information when the VIP is reporting status information at the same time. TICCMR Register write LS-word: D0B0H, Address: MS-word: D0B1H Reset value: 0000H 31 x 23 PLLS 30 29 28 27 CHADR(2:0) 20 x 19 FIL1 18 PDOWN 26 25 FIL 17 LOOP 24 EXLP 16 TX_EN VIPADR(1:0) 22 PD 21 DHEN 15 PLLINT 7 MF_EN 14 13 12 11 10 9 OWIN(2:0) 8 AAC(1:0) 6 5 MODE(2:0) BBC(1:0) 4 3 2 1 RD 0 WR MOSEL(1:0) WR Write Command (S/T, UPN) 0= 1= Data sent in these bits is invalid All configuration bits contain valid data Note: Does not apply to SMINI(2:0) and MSYNC bits RD Read Request to VIP Command Bits (S/T, UPN) 0= Normal operation 168 2003-07-31 Data Sheet PEB 20570 PEB 20571 Register Description 1= DELIC read request of the TICCMR register which was sent to the VIP. It includes initialization and configuration commands and the channel addresses. The VIP returns these values (instead of sending the actual VIP status information) within the IOM-2000 STAT_n_m bit stream. The values are available in the next frame (after next FSC) in DELIC TICSTR register. Note: To avoid blocking, the DELIC must not issue this bit during normal operation. Channel programmed to S/T mode Channel programmed to UPN mode reserved reserved Channel programmed to LT-T mode Note: IOM-2000 cha. 0 and 1 are restricted to the modes LT-S and UPN. This means that MODE(2..0) must not be programmed to the value 001 for these channels. Also see Section 3.2.4.2 on page 58. 011 = 111 = Channel programmed to LT-S mode (point-to-point extended passive bus configuration) or UPN mode or MOSEL(1:0) Interface Mode Selection (S/T, UPN) 00 = 01 = 10 = 11 = MODE(2:0) Mode Configuration (S/T, UPN) 001 = Channel programmed to LT-S mode (short passive bus mode) Note: All other states are reserved. The reset value is 011, e.g. the default mode of VIP is LT-S MF_EN Multiframe Enable (S/T) 0= 1= Multiframes are disabled Multiframes are enabled OWIN(2:0) Oversampling Window Size (S/T, UPN) Specifies the width of the oversampling window in bit samples. The window is centered about the middle of the bit. For example, a size of 16 means that, upon detection of (16/2) = 8 times logical '1', the received bit is detected as '1'. The window size is programmed in steps of two as shown below: 000 = 001 = 010 = 2 4 6 Data Sheet 169 2003-07-31 PEB 20570 PEB 20571 Register Description ... 111 = BBC(1:0) 00 = 10 = 11 = AAC(1:0) 16 Adaptive generation of balancing bit (depending on line delay). upon reception of INFO3 or INFO4 Balancing bit control is disabled, and no balancing bit is added Balancing bit control is disabled, and balancing bit is added after each code violation in the M-bit (INFO3 or INFO4) Adaptive amplifier control in VIP is enabled. The amplifier and the equalizer are switched on/off depending on the level of the received line signal with respect to the comparator threshold. Adaptive amplifier control is disabled. The amplifier and the equalizer are switched off permanently. Adaptive amplifier control is disabled. The amplifier and the equalizer are switched on permanently Programmable deviation disabled Programmable deviation enabled, i.e., the RxPLL reacts only after a certain number of consequent deviations from the PLL controlling range. Transmitter (analog line driver) is disabled (e.g. for nontransparent analog loops in LT-T) Transmitter is enabled (e.g. for switching of transparent analog loops in LT-S) Loops disabled Loop-back enabled. Channel_m transmit data is looped back to the receive data path (either transparent or non-transparent according to state of bit TX_EN). Depending on bit EXLP the loop is closed internally or externally. Note: For UPN additionally bit TUTLR:UTn has to be set to enable the test loop in the DELIC (n= IOM-2000 channel number) Balancing Bit Control (UPN) Adaptive Amplifier Control (S/T, UPN) 00 = 10 = 11 = PLLINT Receive PLL Integrator (UPN) 0= 1= TX_EN Transmitter Enable (S/T, UPN) 0= 1= LOOP Loop-back Mode in VIP Enable (S/T, UPN) 0= 1= PDOWN Power Down Mode (S/T, UPN) 170 2003-07-31 Data Sheet PEB 20570 PEB 20571 Register Description 0= 1= DHEN Operational mode Channel_m in power-down mode (only the level detector in the VIP receiver is in operational mode) D-channel transmitted transparently, without any condition D-channel transmitted transparently if no collision is detected (E=D), if collision is detected (E D) '1s' are transmitted in Dchannel Test filter disable (default setting) Test filter enable (only for test purpose) Phase deviation = (2 bits - 2 oscillator periods + analog delay) Phase deviation = (2 bits - 4 oscillator periods + analog delay) tracking step equals 0.5 oscillator period tracking step equals 1.0 oscillator period No external analog loop. If bit LOOP=1 the loop is closed internally External analog loop. If bit LOOP=1 the loop is closed externally Filter of equalizer inside the VIP receiver disabled Filter of equalizer inside the VIP receiver enabled Command word is dedicated to VIP_n Channel_0 Command word is dedicated to VIP_n Channel_1 Command word is dedicated to VIP_n Channel_2 Command word is dedicated to VIP_n Channel_3 Command word is dedicated to VIP_n Channel_4 Command word is dedicated to VIP_n Channel_5 Command word is dedicated to VIP_n Channel_6 D-channel Handling Enable (LT-T) 0= 1= FIL1 Test Filter enable (applicable only in VIP V2.1 and higher versions) 0= 1= PD Phase Deviation Selection (LT-T) 0= 1= PLLS Receive PLL Adjustment (S/T, UPN) 0= 1= EXLP External Loop (S/T, UPN) 0= 1= FIL Filter Enable (UPN only) 0= 1= CHADR(2:0) Channel_m Address for Commands 000 = 001 = 010 = 011 = 100 = 101 = 110 = Data Sheet 171 2003-07-31 PEB 20570 PEB 20571 Register Description 111 = VIPADR(2:0) 00 = 01 = 10 = 11 = Command word is dedicated to VIP_n Channel_7 Command word is dedicated to VIP_0 Command word is dedicated to VIP_1 Command word is dedicated to VIP_2 Reserved VIP_n Address for Commands Note: Unused bits (x) read as `0'. Data Sheet 172 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.1.6 TRANSIU Initialization Channel Status Register (TICSTR) The Initialization Channel Status Register contains the Command bits to VIP_n, Channel_m mirrored by the VIP in response to a read command issued by the DELIC in the previous frame. Note: The actual Status information from the VIP channels is stored in the data RAM to make it accessible for the DELIC layer-1 state machine software in the DSP. TICSTR Register read Address: LS-word: D0B2H, MS-word: D0B3H Reset value: 0000H 31 x 23 PLLS 15 PLLINT 7 MF_EN 30 29 28 27 CHADR(2:0) 20 x 12 19 x 11 18 PDOWN 10 26 25 FIL 17 LOOP 9 OWIN(2:0) 2 1 RD 0 WR 24 EXLP 16 TX_EN 8 VIPADR(1:0) 22 PD 14 21 DHEN 13 AAC(1:0) 6 5 MODE(2:0) BBC(1:0) 4 3 MOSEL(1:0) Data Sheet 173 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.1.7 Up Test Loop Register The Up Test Loop Register allows to switch an analog loop in the VIP for test purposes. TUTLR Register read/ write Address: LS-word: D0B4H, MS-word: D0B5H Reset value: 0000H 31 x 23 30 x 22 29 x 21 28 x 20 27 x 19 26 x 18 25 x 17 24 x 16 UT(23:16) 15 14 13 12 11 10 9 8 UT(15:8) 7 6 5 4 UT(7:0) 3 2 1 0 UT(n) Up loop back bit for IOM-2000 channel n 0= 1= Up channel is set to normal mode Up channel is set to loop back test mode in the VIP Note: When a channel is programmed to Up loop back test-mode, the TRANSIU expects the frame-start in the receive direction to be detected with very small delay after the frame-start in the transmit direction, and not after 125 us or more (as in normal work mode). Note: To enable the loop in the VIP, additionally TICCMR:LOOP must be set to 1 for the respective channel. Data Sheet 174 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.1.8 Scrambler Mode Register read/write Address: D010H SCMOD Register Reset value: 0003H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 SCMOD2 9 x 1 8 x 0 SCMOD1..0 SCMOD1..0 Scrambling Mode of the UPN Line Interface 00 = Scrambling according to ITU-T V.27 01 = Scrambling compatible to OCTAT-P PEB 2096 10 = DASL scrambler 11 = No scrambling SCMOD2 Scrambler/ Descrambler indication mode (only valid in DELIC V2.3 and higher versions) 0= 1= No "scrambling finished" indication is provided Descrambling is initiated following FSC rising edge "Scrambling finished" indication is provided by register SCSTA. Descrambling is initiated by writing to register SCSTA Data Sheet 175 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.1.9 Scrambler Status Register read/write Address: D011H SCSTA Register Reset value: undefined 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 8 x 0 SCSTA1 SCSTA0 SCSTA0 Descrambler Status 0= Write access: start of descrambling algorithm for all channels enabled in the HRAM (only valid if bit SCMOD2 = 1!) read access: descrambler is processing data Write access: start of scrambling algorithm for all channels enabled in the HRAM read access: descrambling is finished 1= SCSTA1 Scrambler Status (only valid if bit SCMOD2 = 1) 0= 1= read access: scrambler is processing data read access: scrambling is finished Note: Scrambling and descrambling will only work correctly if (in the initialization phase) bit 8 of the OAK register ST2 is set to '1' (See "GHDLCU Frame Frequency" on page 213.) Data Sheet 176 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.2 6.2.2.1 IOMU Register Description IOMU Control Register read/write Address: D040H ICR Register Reset value: 02H 15 x 7 x 14 x 6 x 13 x 5 ICDB 12 x 4 A 11 x 3 OD 10 x 2 DC 9 x 1 DR(1:0) 8 x 0 ICDB Idle Current D-Buffer (for test purpose; only if IOMU is in idle mode: ICR:A = '0') 0= 1= Make frame buffer 0 accessible to the DSP Make frame buffer 1 accessible to the DSP The IOMU is Idle. The state machine of the IOMU is idle, and no accesses to the I-buffer are executed by the IOMU. The IOMU is active, and works according to the programming of the other Control Register bits. Push-Pull mode. Open-Drain mode Single clock (DCL frequency is identical to the IOM-2 data rate) Double clock (DCL frequency is double the IOM-2 data rate) IOM-2 data rate of 1 x 384 kbit/s (1 x 6 time slots/frame) IOM-2 data rate of 1 x 768 kbit/s (1 x 12 time slots/frame) IOM-2 data rate of 2 x 2.048 Mbit/s (2 x 32 time slots/frame) (default) IOM-2 data rate of 1 x 4.096 Mbit/s (1 x 64 time slots/frame) 177 2003-07-31 A IOMU Activation 0= 1= OD DD0 and DD1 Output Mode 0= 1= DC Double Data Rate Clock 0= 1= DR(1:0) IOM-2 Data Rate 00 = 01 = 10 = 11 = Data Sheet PEB 20570 PEB 20571 Register Description 6.2.2.2 IOMU Status Register read Address: D041H ISR Register Reset value: undefined 15 IBUFF 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 x 8 x 0 x IBUFF I-Buffer Index Note: Used for testing. May also be used in double data rate mode of the IOMU to determine if the IOMU buffers have been swapped already 0= 1= Buffer 0 is currently used as I-buffer, buffer 1 is used as D-buffer Buffer 1 is currently used as I-buffer, buffer 0 is used as D-buffer Note: (x) unused bits read as '0' Data Sheet 178 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.2.3 IOMU Tri-State Control Register read/write Address: Set Address: D042H Reset Address: D043H Read Address: D044H ITSCR Register Reset Value: 00H 15 14 13 12 11 10 9 8 TS(15:8) 7 6 5 4 TS(7:0) 3 2 1 0 TS(15:0) Every bit determines whether DD0/1 output is in tri-state during the time slot sequence. The time slot sequence length, indices and port controlled by each TS-bit is defined according the IOMU data rate mode (ICR.DR(1:0)) 0= 1= DD0/1 is in tri-state during the related time slot sequence DD0/1 is driven by the IOMU during the related time slot sequence Data Sheet 179 2003-07-31 PEB 20570 PEB 20571 Register Description Table 62 ITSCR Bit TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 Tristate Control Assignment for IOM-2 Time Slots 1 x 6 TS/frame DD0 DD0 DD0 DD0 DD0 DD0 DD0 not used not used not used not used not used not used not used not used not used not used 0 1 2 3 4 5 TS 1 x 12 TS/frame DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 not used not used not used not used 0 1 2 3 4 5 6 7 8 9 10 11 TS 2 x 32 TS/frame DD0/1 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD1 DD1 DD1 DD1 DD1 DD1 DD1 DD1 TS 0-3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 0-3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 1 x 64 TS/frame DD0/1 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 DD0 TS 0-3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 32-35 36-39 40-43 44-47 48-51 52-55 56-59 60-63 Data Sheet 180 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.2.4 IOMU DRDY Register read 13 0 5 12 0 4 DS(7:0) 11 0 3 10 0 2 Address: D045H 9 0 1 8 0 0 IDRDYR Register Reset value: undefined 15 0 7 14 0 6 bit DRDY Sample DSx indicates the availability of the D-channels of the previous frame. 0 = STOP (D-channel blocked due to collision), 1 = GO e.g. DS1 was sampled during the D-channel of IOM-2 channel 1, etc. DS0 DS1 DS2 DS3 DS4 DS5 DS6 DS7 corresponds to D-channel of IOM-2 port 0 cha 0 corresponds to D-channel of IOM-2 port 0 cha 1 corresponds to D-channel of IOM-2 port 0 cha 2 corresponds to D-channel of IOM-2 port 0 cha 3 corresponds to D-channel of IOM-2 port 0 cha 4 corresponds to D-channel of IOM-2 port 0 cha 5 corresponds to D-channel of IOM-2 port 0 cha 6 corresponds to D-channel of IOM-2 port 0 cha 7 Note: In 1 x 4.096 Mbit/s mode (i.e.16 IOM-2 channels/frame), DRDY is sampled only during the D-channels of the first eight IOM-2 channels of every frame. Data Sheet 181 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.2.5 IOMU Data Prefix Register read/write 14 13 12 11 10 Address: D046H 9 8 IDPR Register Reset value: E0H 15 IDP(7:0) 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x IDP(7:0) IOMU Data Prefix Determines the high byte of every word being read from the IOM circularbuffer (I-buffer or D-buffer). The low byte is the data being read from the circular buffer. After reset this register contains the MSB of the base address of the A-lawto-linear ROM table: E0H. Note: (x) unused bits read as '0' Data Sheet 182 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.3 6.2.3.1 PCMU Register Description PCMU Command Register read/write 13 x 5 SFH 12 x 4 ICDB 11 x 3 PA 10 x 2 PDCL Address: D060H 9 x 1 8 x 0 PCR Register Reset value: 0000H 15 x 7 x 14 x 6 x PDR(1:0) PDR(1:0) PCM Data Rate 00 = 01 = 10 = 11 = PDCL 2.048 Mbit/s (port 0..3) 4.096 Mbit/s (port 0, 2) 8.092 Mbit/s (port 0) 16.384 Mbit/s (1 x 256 time slots per frame, if only first or second half of 8 kHz frame is handled) (port 0) Single Data Rate Clock Double Data Rate Clock The PCMU is in idle mode The PCMU is in active mode PCM Double Data Rate Clock 0= 1= PA PCMU Activation 0= 1= ICDB Idle Current D-Buffer Used only for testing of PCMU in IDLE mode (PCR:PA = '0') to determine which buffer is being accessed by the DSP 0= 1= Frame buffer 0 is accessed by the DSP Frame buffer 1 is accessed by the DSP SFH Second Frame Half Applicable only in 16.384 Mbit/s data rate mode 0= 1= The first 128 time slots of each frame are handled by the PCMU The second 128 time slots of each frame are handled by the PCMU Note: 'x' = unused (read as '0') Data Sheet 183 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.3.2 PCMU Status Register read Address: D061H PSR Register Reset value: undefined 15 PBUFF 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 x 8 x 0 x PBUFF P-Buffer Index Note: Used for testing. May also be used in double data rate mode of the PCMU to determine if the PCMU buffers have been swapped already 0= 1= Buffer 0 is currently used as P-buffer, buffer 1 is used as D-buffer Buffer 1 is currently used as P-buffer, buffer 0 is used as D-buffer Note: (x) unused bits read as '0' Data Sheet 184 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.3.3 PCMU Tri-state Control Registers read/write (set/reset) read Address: D062-63H set Address: D062H reset Address: D063H read Address: D064-65H set Address: D064H reset Address: D065H read Address: D066-67H set Address: D066H reset Address: D067H read Address: D068-69H set Address: D068H reset Address: D069H read Address: D06A-6BH set Address: D06AH reset Address: D06BH PTSC0 Register PTSC1 Register read/write (set/reset) PTSC2 Register read/write (set/reset) PTSC3 Register read/write (set/reset) PTSC4 Register read/write (set/reset) Data Sheet 185 2003-07-31 PEB 20570 PEB 20571 Register Description PTSC5 Register read/write (set/reset) read Address: D06C-6DH set Address: D06CH reset Address: D06DH read Address: D06E-6FH set Address: D06EH reset Address: D06FH read Address: D070-71H set Address: D070H reset Address: D071H PTSC6 Register read/write (set/reset) PTSC7 Register read/write (set/reset) Reset values (PTSC0..7): 0000H 15 14 13 12 11 10 9 8 PTSCn(15:8) 7 6 5 4 3 2 1 0 PTSCn(7:0) PTSCn (15..0) Tristate Control for each PCM Time Slot 0= 1= The controlled time slot is invalid The controlled time slot is valid Data Sheet 186 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.3.4 PCMU Data Prefix Register read/write Address: D072H PDPR Register Reset value: E0H 15 14 13 12 11 10 9 8 PDP(7:0) 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x PDP(7:0) PCMU Data Prefix The data written to this register is read as the most significant byte of every time slot read by the DSP from the PCMU frame buffers. Can be used for quick access to the a/-law ROM, for conversion of compressed data (received via the PCM interface) into linear value. After reset this register contains the MSB of the base address of the a-lawto-linear ROM table: E0H. To enable quick conversion from -law to linear, the PCMU Data Prefix Register should be programmed to E1H. Note: (x) unused bits read as '0' Data Sheet 187 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.4 6.2.4.1 A-/-law Unit Register Description A/-law Unit Control Register Address: D020H A/-law Unit Control Register (AMCR) read/write Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 x 8 x 0 MODE Note: 'x' = unused bits This register controls the conversion mode of the A/-law unit MODE A/-law Mode Programming 0= 1= Conversion from linear value to A-law value (default) Conversion from linear value to -law value Data Sheet 188 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.4.2 A/-law Input Register write Address: D021H A/-law Unit Input Register (AMIR) Reset value: undefined 15 14 13 12 11 10 9 8 IND(15:8) 7 6 5 4 IND(7:0) Note: - In -law mode, only the 14 MSBs are processed. - In A-law mode, only the 13 MSBs are processed. IND(15:0) Linear Input Data Provides the linear input data that is to be converted into logarithmic data format according to A-law or -law algorithm. 3 2 1 0 Data Sheet 189 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.4.3 A/-law Output Register Address: D022H A/-law Unit Output Register (AMOR) read Reset value: undefined 15 x 7 14 x 6 13 x 5 12 x 4 11 x 3 10 x 2 9 x 1 8 x 0 OUTD(7:0) Note: 'x' = unused bits, driven to '0' OUTD(7:0) Logarithmic Output Data Provides the logarithmic output data generated by the A/--law unit out of the linear input data. The data format (A-law or -law) depends on the the selected conversion algorithm. Data Sheet 190 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.5 6.2.5.1 HDLCU Registers Description HDLCU Control Register In order to enable DSP access all the buffers and RAMS, DSPCTRL bit must be set to `1'. HCR Register Reset value: 0001H 15 x 7 x 14 BITOR 6 13 x 5 12 x 4 11 x 3 10 x 2 9 x 1 8 x 0 DSPCTRL write Address: D180H HPRS(5:0) BITOR Determines the order of bits inside one HDLC data byte 0= 1= HDLC data is transmitted/ received with MSB first (default) HDLC data is transmitted/ received with LSB first HPRS(5:0) DSPCTRL HDLCU Channel Preset The number of HDLC channels to be processed by the HDLCU DSP Access Control to the HDLCU 0= 1= The DSP must not access the HDLCU buffers and RAMs The DSP may access the HDLCU buffers Note: Each time DSPCTRL is set, HPRS is also set. Data Sheet 191 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.5.2 HDLCU Status Register read Address: D180H HSTA Register Reset value: 0001H 15 HHOLD 7 CHCNT(0) 14 BITOR 6 13 x 5 12 11 10 CHCNT(5:1) 9 8 4 3 2 1 0 DSPCTRL HPRS(5:0) DSPCTRL DSP Access Control to the HDLCU 0= 1= The HDLCU is currently processing the channel The DSP is currently accessing the HDLCU Number of HDLC channels handled by the HDLCU (max. 32) HPRS(5:0) CHCNT(5:0) HDLC Channel Preset Channel Count Number of channels that have already been processed in the current frame BITOR Bitorder Determines the order of bits inside an HDLC data byte going to (coming from) the IOMU, PCMU or TRANSIU. 0= 1= HDLC data is transmitted with MSB first HDLC data is transmitted with LSB first HDLCU is processing the current frame HDLCU has finished processing the current frame HHOLD HDLCU Busy Indicator 0= 1= Data Sheet 192 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.5.3 Channel Command Vector read/ write Address: 4040H - 405FH HCCV Registers Each of the 32 HDLC channels has a 7-bit command vector that resides in the corresponding address of the command RAM. The structure of a command vector is as follows: 15 x 7 x 14 x 6 DBSEL 13 x 5 RECRES 12 x 4 11 x 3 TXCMD(2:0) 10 x 2 9 x 1 CRC 8 x 0 IDLE Note: Accesses to these registers are possible only if register bit HCR:DSPCTRL = 1 'x' = unused DBSEL D- or B-Channel Select 0= 1= Indication for a B-channel. HDLC protocol is performed on all 8 data bits Indication for a D-channel. HDLC protocol is performed only on the 2 MSB data bit in the Receive Input Buffer and Transmit Output Buffer Normal operation Reset the HDLC receiver End transmission Start transmission at the first bit of the D-channel Start transmission at the second bit of the D-channel Start transmitting a flag (beginning with the fifth bit of the flag, since '0111' is automatically inserted) Abort transmission Note: other combinations are reserved CRC CRC Enable 0= Data Sheet RECRES Receiver Reset 0= 1= TXCMD(2:0) Transmit Command 000= 001= 010= 011= 100= CRC checking algorithm off 193 2003-07-31 PEB 20570 PEB 20571 Register Description 1= IDLE 0= 1= CRC checking algorithm on Transmit 'ones' over an idle channel (no shared flag are possible in this mode) Transmit 'flags' over an idle channel (shared flags are supported ) Note: In the receive direction, the only function of the command vector is to indicate whether the channel is a D-channel or a B-channel, and whether to use CRC decoding or not. The main function of the command vector is to control the flow of time slots in the transmit direction. Inter Frame Timefill IDLE Mode Data Sheet 194 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.5.4 Channel Status Vector read Addresses: 40A0H - 40BFH HCSV Registers Reading a channel from the Receive Output Buffer and Writing to a channel in the Transmit Input Buffer is done according to the channel's status vector in the Transmit Output Buffer. This vector contains 7 flags: 15 x 7 x 14 x 6 FLAG 13 x 5 EMPTY 12 x 4 FULL 11 x 3 ABORT 10 x 2 STOP 9 x 1 CRC 8 x 0 NO Note: Accesses to these registers are possible only if register bit HCR:DSPCTRL = 1 'x' = not used NO Not Octet 0= 1= CRC 0= 1= STOP 0= 1= Normal operation The last bits of a message have not filled an octet (8 bits) No CRC error in received message CRC error was detected in the received message Normal operation HDLCU has detected an end of message flag in the receive direction. The DSP must read the octet in the Receive Output Buffer before the next message start flag is detected Normal operation The DSP has detected an incoming abort message (7 consecutive '1s'). The STOP flag is also set to 1. This means that the DSP should ignore the current message being transmitted over the channel in question and report to the external micro controller CRC Error Stop Indication ABORT Abort Indication 0= 1= FULL Data Sheet Receive Buffer Full Indication 195 2003-07-31 PEB 20570 PEB 20571 Register Description 0= 1= Normal operation Indicates that the Receive Output Buffer has a newly processed octet in it. The DSP must read this octet before starting the next processing session, otherwise it might be lost. The transmit buffer is full. The transmit buffer is empty. The current time slot in the Transmit Input Buffer has been fully processed by the HDLCU. The Transmit Input buffer is ready to receive the next octet of the message by the DSP. Note: The DSP must put a new octet into the buffer before starting the next processing session, otherwise the same octet will be read again. FLAG Status Vector Flag 0= 1= Ignore the status vector and do not read or write on this channel Read the channel's status vector and process accordingly Note: FLAG will go to `1' as soon as EMPTY or FULL go to `1'. EMPTY Transmit Buffer Empty 0= 1= Data Sheet 196 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6 6.2.6.1 GHDLC Register Description GHDLC Test/ Normal Mode Register read/write Address: D0C0H GTEST Register Reset value: 0001H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 x 8 x 0 TEST CHMOD1..0 Channel Mode 0= 1= Normal operation mode Test mode Note: As GTEST has a reset value of 01H this register has to set to 0 to enable the GHDLCU Data Sheet 197 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.2 GHDLC Channel Mode Register read/write Address: D0C1H GCHM Register Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 8 x 0 CHMOD(1..0) CHMOD1..0 Channel Mode 00 = Channel 0 used for up to 8.192 MHz (DELIC-PB only) Channel 0 used for up to 2.048 MHz (DELIC-LC) GHDLC buffer size = 32 bytes 01 = 2 channels (ch 0+3) used for up to 2.048 MHz GHDLC buffer size = 2 x 16 bytes Note: DELIC-PB only 10 = 4 channels (ch 0..3) used up to 2.048 MHz GHDLC buffer size = 4 x 8 bytes Note: DELIC-PB only 11 = Reserved Data Sheet 198 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.3 GHDLC Interrupt Register read Address: D0D4H GINT Register Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 INT3 10 x 2 INT2 9 x 1 INT1 8 x 0 INT0 INTn bits Interrupt Indication for GHDLC Channel n (= 0..3) 0= 1= Normal operation GHDLC interrupt has occurred Note: INT0-INT3 are reset by a read access to this register Note: For GCHM:CHMOD = 00 (cha. 0 up to 8 MBit/s) only INT0 is used For GCHM:CHMOD = 01 (cha. 0 and 3 up to 2 MBit/s) only INT0, INT3 are used. For GCHM:CHMOD = 10 (cha. 0..3 up to 2 MBit/s) all bits are used Data Sheet 199 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.4 GHDLC FSC Interrupt Control Register read Address: D0D3H GFINT Register Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 FINT3 10 x 2 FINT2 9 x 1 FINT1 8 x 0 FINT0 FINTn FSC Interrupt Control GHDLC Channel n (= 0..3) 0= The rising edge of a 62.5 s/ 10s frame causes a receiver interrupt only if a full interrupt has not occurred during the previous frame The rising edge of a 62.5 s/ 10s frame causes a receiver interrupt regardless whether or not a full interrupt occurred during the previous frame 1= Note: The interrupt frequency can be set in register ST2 (Chapter 6.2.6.15). Data Sheet 200 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.5 GHDLC Receive Channel Status Registers 0..3 read read read read Address: Address: Address: Address: D0C2H D0C3H D0C4H D0C5H GRSTA Register 0 GRSTA Register 1 GRSTA Register 2 GRSTA Register 3 Reset value: 001FH 15 x 7 EMPTY 14 x 6 OVER 13 x 5 FULL 12 x 4 11 x 3 10 x 2 RBFILL(4:0) 9 COLLD 1 8 UNDER 0 RBFILL(4:0) Receive Buffer Fill Indicates to the DSP the currently available number of bytes - 1 in the receive buffer FULL Receive Buffer Full 0= 1= No receive buffer full indication Receive buffer block of the GHDLC is full. The blocks have been switched. No buffer overrun indication Two consecutive full interrupts were received without a GHDLC access to the status register in between, i.e. a buffer was missed. No transmit buffer empty indication The transmit buffer block currently being transmitted over the GHDLC channel has been emptied No buffer underrun indication A buffer containing an incomplete message has been emptied without a continuation of the message in the other buffer OVER Buffer Overrun 0= 1= EMPTY Transmit Buffer Empty 0= 1= UNDER Buffer Underrun 0= 1= Data Sheet 201 2003-07-31 PEB 20570 PEB 20571 Register Description COLLD Collision Detected 0= 1= No collision detection indication Collision detected during transmission. The message needs to be re-sent. Note: Only relevant in HDLC-Mode, if one device does not operate conform to the HDLC protocol definition Note: Reading the register GRSTA resets its bits to the default value. Data Sheet 202 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.6 GHDLC Receive Data and Status read 14 END 6 13 CRC 5 12 NO 4 11 x 3 Address: 2040H -207FH 10 x 2 9 x 1 8 x 0 To each data byte in the receive buffer 4 flag bits are appended RXDAT Registers 15 ABORT 7 RDAT7..0 NO Not Octet 0= 1= Received message is a multiple of eight bits Received message is not a multiple of eight bits Received byte contains no CRC error flag. Received byte contains a CRC error flag. A CRC error was detected in the received frame. CRC CRC Error Flag 0= 1= END END Flag 0= 1= Received byte contains no END flag Received byte contains an END flag Received byte contains no ABORT flag Received byte contains an ABORT flag ABORT ABORT Flag 0= 1= RD7..0 Received data byte Data Sheet 203 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.7 GHDLC Mode Registers read/write read/write read/write read/write Address: Address: Address: Address: D0C6H D0C7H D0C8H D0C9H GMOD Register 0 GMOD Register 1 GMOD Register 2 GMOD Register 3 Reset value: 0140H 15 x 7 CLASS 14 x 6 COLLD 13 x 5 PPOD 12 x 4 IFTF 11 GEM 3 10 GEDGE 2 9 EDGE 1 8 TE 0 OPMOD(1:0) CRCMOD(1:0) CRCMOD (1:0) CRC Mode 00 = 01 = 10 = 11 = CRC algorithm disabled 16-bit CRC algorithm (X16+X12+X5+1) 32-bit CRC algorithm (X31+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X1+1) reserved OPMOD(1:0) Operational Mode Programs the mode of the GHDLC channel Note: Every channel of GHDLC, that is not in use, should be programmed to Async mode (OPMOD = "10"), in order to prevent any access of the idled channels to the GHDLC buffers. For example, if GHDLC channel mode register CHMOD = "00" (operation only of channel 0) then OPMOD field in registers GMOD 1/2/3 should be set to "10" (Async mode) 00 = 01 = 10 = 11 = IFTF 0= Data Sheet HDLC mode Extended transparent mode Asynchronous mode (enables accesses to register GASYNC) reserved Sequence of '1s' is used as interframe time fill characters 204 2003-07-31 Interframe Time Fill PEB 20570 PEB 20571 Register Description 1= PPOD 0= 1= COLLD 0= 1= CLASS Flags (7EH) are used as interframe time fill characters Open-drain Push-pull Collision detection disabled Arbitration between several GHDLC on a bus is done using collision detection Channel has priority class 8 Channel has priority class 10 Transmit line is only enabled during the transmission of a message including opening and closing flags Transmit line is always enabled Receiver samples data on rising edge of the line clock Receiver samples data on falling edge of the line clock Receiver samples data on rising edge of the line clock Receiver samples data on falling edge of the line clock Normal Operation GEDGE is disabled, EDGE is used for sampling the data. 1= Enhanced Operation GEDGE is enabled, EDGE has to be programmed to the opposite of GEDGE. Note: The enhanced mode ensures proper handling of Interframe time fill (ITF) flags with shared '0' (please refer to Figure 50). In enhanced operation an additional delay of 15 s is added to the received data. Push-Pull / Open-Drain Configuration Collision Detection Priority Class Assignment 0= 1= TE Transmit Enable 0= 1= EDGE Edge Programming for Receive Data Sampling 0= 1= GEDGE Edge Programming for GHDLC Receive Data Sampling 0= 1= GEM GHDLC Enhanced Mode 0= Data Sheet 205 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.8 GHDLC Channel Transmit Command Registers write write write write Address: Address: Address: Address: D0CAH D0CCH D0CEH D0D0H GTCMD Register 0 GTCMD Register 1 GTCMD Register 2 GTCMD Register 3 Reset value: 0000H 15 x 7 x 14 x 6 STOP 13 x 5 TXCMD 12 x 4 11 x 3 10 x 2 TBFILL(4:0) 9 x 1 8 x 0 TBFILL(4:0) Transmit Buffer Fill Indicates to the GHDLC unit the currently available number of bytes - 1 in the transmit buffer. Transmission Command 0= 1= Transmission is not started Start transmission Message continues in the next buffer End of the message is in this buffer TXCMD STOP Stop Command 0= 1= Data Sheet 206 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.9 ASYNC Control Register read/ write Address: D0D2H GASYNC Register Reset value: 0000 15 x 7 14 x 6 13 x 5 12 x 4 11 x 3 10 x 2 9 x 1 8 x 0 IOPORT(7..0) Accesses to register GASYNC: IOPORT Writing a "1" to the bit position bits sets the port pin below bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 LTXD0 LTXD1 LTXD2 LTXD3 LRTS0 LRTS1 LRTS2 LRTS3 Reading from the bit position indicates the current state of the port pin below LRXD0 LRXD1 LRXD2 LRXD3 LCTS0 LCTS1 LCTS2 LCTS3 Accesses to the different bits of this register are only possible in ASYNC mode of the corresponding GHDLC channel (See "GHDLC Mode Registers" on page 204.). Note: GHDLC channels 3,2,1 are only accessible, if the respective bits in register MUXCTRL are set. Data Sheet 207 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.10 LCLK0 Control Register LCLK0 Control Register (GLCLK0) Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 LCLK0EN 9 x 1 8 x 0 read/write Address: D08AH LCLK0(1:0) Note: 'x' = unused bits, read as 0 . LCLK0EN LCLK0 Output Enable 0= 1= LCLK0 is input (default) LCLK0 is driven outward via LCLK0 pin LCLK0(1:0) LCLK0 Output Clock Rate Note: This option is valid only when LCLK0 is output. When LCLK0 is input the frequency is determined externally. 00 = 01 = 10 = 11 = 2.048 MHz (default) 4.096 MHz 8.192 MHz 16.384 MHz Data Sheet 208 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.11 LCLK1 Control Register LCLK1 Control Register (GLCLK1) Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 LCLK1EN 9 x 1 8 x 0 read/write Address: D08BH LCLK1(1:0) Note: 'x' = unused bits, read as 0 . LCLK1EN LCLK1 Output Enable 0= 1= LCLK1 is input (default) LCLK1 is driven outward via LCLK1 pin LCLK1(1:0) LCLK1 Output Clock Rate Note: This option is valid only when LCLK1 is output. When LCLK1 is input the frequency is determined externally. 00 = 01 = 10 = 11 = 2.048 MHz (default) 4.096 MHz 8.192 MHz 16.384 MHz Data Sheet 209 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.12 LCLK2 Control Register LCLK2 Control Register (GLCLK2) Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 LCLK2EN 9 x 1 8 x 0 read/write Address: D08CH LCLK2(1:0) Note: 'x' = unused bits, read as 0 . LCLK2EN LCLK2 Output Enable 0= 1= LCLK2 is input (default) LCLK2 is driven outward via LCLK2 pin LCLK2(1:0) LCLK2 Output Clock Rate Note: This option is valid only when LCLK2 is output. When LCLK2 is input the frequency is determined externally. 00 = 01 = 10 = 11 = 2.048 MHz (default) 4.096 MHz 8.192 MHz 16.384 MHz Data Sheet 210 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.13 LCLK3 Control Register LCLK3 Control Register (GLCLK3) Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 LCLK3EN 9 x 1 8 x 0 read/write Address: D08DH LCLK3(1:0) Note: 'x' = unused bits, read as 0 . LCLK3EN LCLK3 Output Enable 0= 1= LCLK3 is input (default) LCLK3 is driven outward via LCLK3 pin LCLK3(1:0) LCLK3 Output Clock Rate Note: This option is valid only when LCLK3 is output. When LCLK3 is input the frequency is determined externally. 00 = 01 = 10 = 11 = 2.048 MHz (default) 4.096 MHz 8.192 MHz 16.384 MHz Data Sheet 211 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.14 Muxes Control Register MUXCTRL Register Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 PMUX1 9 x 1 PMUX0 8 x 0 IMUX OAK: read/write Address: D14AH IMUX 0= 1= IOM-2000 pins are used for the IOM-2000 interface IOM-2000 pins are used for the GHDLC cha. 1 PMUX0 0= 1= PCM ports 0 & 2 pins are used for PCM PCM ports 0 & 2 pins are used for GHDLC cha. 2 PMUX1 0= 1= PCM ports 1 & 3 pins are used for PCM PCM ports 1 & 3 pins are used for GHDLC cha. 3 Data Sheet 212 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.6.15 GHDLCU Frame Frequency ST2 Register Reset value: xxxx xx00 xxxx xxxxB 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 8 OAK: write Address: DSP-register OUSER1 OUSER0 1 x 0 x OUSER1 0= 1= 16 kHz GHDLCU frame frequency 96 kHz GHDLCU frame frequency OUSER0 0= Test mode write access to HRAM-0 is enabled write access to HRAM-1, HRAM-2 is disabled 1= 1) write access to HRAM0, HRAM-1, HRAM-2 is enabled1) This bit has to be set once during initialization for single scrambling mode. If mixed scrambling mode is used (e.g. DASL/OCTAT-P) the following has to be done: When accessing the HRAM this bit has to be reset ('0') before enabling descrambler/scrambler it has to be set ('1'). Data Sheet 213 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.7 6.2.7.1 DCU Register Description Interrupt Mask Register read/write Address: D002H IMASK Register Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 x 8 x 0 IMASK IMASK GHDLC Interrupt Mask 0= 1= GHDLC interrupt disabled GHDLC interrupt enabled Note: The unused bits (x) are read as `0'. Data Sheet 214 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.7.2 Status Event Register read Address: D003H STEVE Register Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 PFS 9 x 1 FSC 8 x 0 FP PFS PFS Status Bit 0= 1= normal operation PFS rising edge has occurred (reset by DSP read access) normal operation FSC rising edge has occurred (reset by DSP read access) normal operation Both FSC and PFS rising edges have occurred, i.e. bits PFS and FSC are set (reset by DSP read access) FSC FSC Status Bit 0= 1= FP FSC & PFS Status Bit 0= 1= Note: Unused bits ('x') are read as `0'. Data Sheet 215 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.7.3 Statistics Counter Register read/write Address: D004H STATC Register Reset value: unchanged Reset value: unchanged upon chip reset, but reset upon FSC detection if STATC was read by the DSP since last occurence of FSC. 15 x 7 14 x 6 13 x 5 12 x 4 11 x 3 10 x 2 9 x 1 8 x 0 STATC(7:0) STATC (7:0) Statistics Counter Value Note: The unused bits (x) are read as `0'. Data Sheet 216 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.7.4 Statistics Register read/write Address: D005H STATI Register Reset value: 0000H 15 x 7 14 x 6 13 x 5 12 x 4 11 x 3 10 x 2 9 x 1 8 x 0 MSC(7:0) MSC(7:0) Max. Statistics Count Note: The unused bits (x) are read as `0'. Data Sheet 217 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.8 6.2.8.1 P Configuration Registers P Interface Configuration Register DSP: read P: read/write MCFG Register D148H DSP Address: P high address: none P low address: 48H Reset value: 00H 15 x 7 DRQLV 14 x 6 IRQLV 13 x 5 IRQMO 12 x 4 IMASK 11 x 3 IACK 10 x 2 PEC 9 x 1 FB 8 MODE 0 DMA DMA DMA Mode Enabled 0= 1= No DMA DMA enabled Memory-to-memory mode used for DMA transfers Fly-by mode used for DMA transfers No PEC Transfers PEC transfers are supported (for connection of C16x P) Interrupt vector is provided to CPU after 1st IACK pulse. Interrupt vector is provided to CPU after 2nd IACK pulse. IREQ pin is disabled IREQ pin is enabled Open-drain mode FB Fly-by Mode 0= 1= PEC PEC Transfers Enable 0= 1= IACK Interrupt Acknowledge Mode 0= 1= IMASK Interrupt Mask 0= 1= IRQMO IREQ Pin Mode 0= Data Sheet 218 2003-07-31 PEB 20570 PEB 20571 Register Description 1= IRQLV 0= 1= DRQLV 0= 1= MODE Push-pull mode Low active High active High active Low active IREQ Pin Level DREQR/DREQT Pins Level P Interface Mode Contains the value of MODE input pin sampled by rising edge of RESET Note: This signal is hardwired. 0= 1= Intel/Siemens mode Motorola mode Data Sheet 219 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.8.2 Interrupt Vector Register DSP: read/ write P: read IVEC Register D168H DSP Address: P high address: none P low address: 68H Reset value: unchanged 7 6 5 4 3 2 1 0 IVEC(7:0) IVEC7..0 Interrupt vector Contains the interrupt vector address that is output during an INTA cycle of the P Data Sheet 220 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.9 6.2.9.1 P Mailbox Registers Description P Command Register DSP: read P: write MCMD Register D140H DSP address: P address: 40H Reset value: 00H 7 6 5 4 MCMD 3 2 1 0 MCMD P Command Contains the P command (8-bit opcode) to the DELIC. Data Sheet 221 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.9.2 P Mailbox Busy Register DSP: write P: read MBUSY Register D141H DSP Address: P high address: 41H P low address: none Reset value: 00H 15 MBUSY 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 x 8 x 0 x MBUSY P Mailbox Busy Bit 0= 1= Mailbox is available for the external P. The P may write a command to MCMD. Mailbox is blocked for the external P. The P may not write a command to MCMD. Note: MBUSY is automatically set each time a command is written to MCMD by the P. MBUSY is reset automatically by a direct OAK write operation to the MBUSY register. Data Sheet 222 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.9.3 P Mailbox Generic Data Register DSP: read DSP Address: DSP high: D143H DSP low: D142H P high: 43H P low: 42H MGEN Register D144H P: write Reset value: unchanged 15 14 13 12 11 10 9 8 MGEN(15..8) 7 6 5 4 3 2 1 0 MGEN(7..0) MGEN (15..0) P Mailbox Generic Data (16 bits) Data Sheet 223 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.9.4 P Mailbox (General and DMA Mailbox) Data Registers DSP: read P: write MDTn Register (n=0..7) on page 156 TDTn/ MDTn+8 Register (n=0..7) Reset value: unchanged 15 14 13 Addr. see table 12 11 10 9 8 MDTn(15..8) 7 6 5 4 3 2 1 0 MDTn(7..0) MDTn (15..0) P Mailbox Data (each byte is addressed separately by the external P) Note: The 16 data registers (MDT1..7, TDT0/MDT8..TDT7/MDT15) have the same structure. The addresses are displayed in the register map (page 156, page 158). Data Sheet 224 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.9.5 DSP Command Register DSP: write P: read OCMD Register D160H DSP address: P address: 60H Reset value: 00H 7 6 5 4 OCMD 3 2 1 0 OCMD DSP Command Contains the DSP command/ indication (8-bit opcode) to the DELIC. Data Sheet 225 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.9.6 DSP Mailbox Busy Register DSP: read P: read/ write OBUSY Register D161H DSP Address: P high address: 61H P low address: none Reset value: 00H 15 OBUSY 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 x 8 x 0 x OBUSY DSP Mailbox Busy Bit 0= 1= Mailbox is available for the DSP. The DSP may write a command/ indication OCMD. Mailbox is blocked for the DSP. The DSP may not write a command/ indication to OCMD. Note: OBUSY is automatically set each time a command/ indication is written to OCMD by the DSP. OBUSY is reset automatically by a direct P write operation to the OBUSY register Data Sheet 226 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.9.7 DSP Mailbox Generic Data Register DSP: write DSP address: DSP high: D163H DSP low: D162H P high: 63H P low: 62H OGEN Register D164H P: read Reset value: unchanged 15 14 13 12 11 10 9 8 OGEN(15..8) 7 6 5 4 3 2 1 0 OGEN(7..0) OGEN 15..0 DSP Mailbox Generic Data (16 bits) Data Sheet 227 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.9.8 DSP Mailbox (General and DMA Mailbox) Data Registers DSP: write P: read ODTn Register (n= 0..15) RDTn/ ODTn+8 Register (n=0..7) Reset value: unchanged 15 14 13 Addr. on page 158 12 11 10 9 8 ODTn(15..8) 7 6 5 4 3 2 1 0 ODTn(7..0) ( ODTn (15..0) DSP Mailbox Data (each byte is addressed separately by the external P) Note: The 16 data registers (ODT1..7, RDT0/ODT8..RDT7/ODT15) have the same structure. The addresses are displayed in the register map (page 156, page 158). Data Sheet 228 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.10 DMA Mailbox Registers Description 6.2.10.1 DMA Mailbox Transmit Counter Register DTXCNT Register Reset value: 000FH 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 10 x 2 9 x 1 8 x 0 DSP: read/write Address: D150H TXCNT(3:0) Note: Writing to TXCNT initiates a DMA transfer of TXCNT+1 bytes to the DMA Tx Mailbox. TXCNT is decremented with every DMA cycle. When all bytes have been transmitted TXCNT has the value 'F'. TXCNT(3..0) Number of bytes to be transmitted minus 1 Data Sheet 229 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.10.2 DMA Mailbox Receive Counter Register DRXCNT Register Reset value: 000FH 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 10 x 2 9 x 1 8 x 0 DSP: read/write Address: D170H RXCNT(3:0) Note: Writing to RXCNT initiates a DMA transfer of RXCNT+1 bytes to the DMA Rx Mailbox. RXCNT is decremented with every DMA cycle. When all bytes have been transmitted RXCNT has the value 'F'. RXCNT(3..0) Number of bytes to be received minus 1 Data Sheet 230 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.10.3 DMA Mailbox Interrupt Status Register DINSTA Register Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 TINT 10 x 2 RINT 9 x 1 TMSK 8 x 0 RMSK DSP: read/ write Address: D152H Contains the status of the DMA Mailbox. The bits in this register are reset by a read access to register DINSTA. TINT Transmit Interrupt from DMA Mailbox (Read only) 0= 1= RINT No transmit interrupt from DMA-mailbox occurred The DMA-controller has finished to write the requested number of bytes to the DMA-mailbox. No transmit interrupt from DMA-mailbox occurred The DMA-controller has finished to read the requested number of bytes from the DMA-mailbox. Disable transmit interrupt Enable transmit interrupt Disable receive interrupt Enable receive interrupt Receive Interrupt from DMA Mailbox (Read only) 0= 1= TMSK Transmit Interrupt Mask (Read/ Write) 0= 1= RMSK Receive Interrupt Mask (Read/ Write) 0= 1= Data Sheet 231 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11 Clock Generator Register Description 6.2.11.1 PDC Control Register PDC Control Register (CPDC) Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 8 x 0 read/write Address: D080H PDC(1:0) Note: 'x' = unused bits, read as 0 . PDC(1:0) PDC Frequency Selection (Only in Master Mode when PDC is output) 00 = 01 = 10 = 11 = PDC = 2.048 MHz (default) PDC = 4.096 MHz PDC = 8.192 MHz PDC = 16.384 MHz Data Sheet 232 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.2 PFS Control Register PFS Control Register (CPFS) Reset value: 0001H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 x 8 x 0 PFS read/write Address: D081H Note: 'x' = unused bits, read as 0 . PFS PFS Frequency Selection (Selectable in Slave mode when PFS is input; in Master mode PFS = 8 kHz) 0= 1= PFS = 4 kHz PFS = 8 kHz (default) Note: When the PFS is output, its frequency is always 8 kHz, therefore this bit should be left in its reset-value ('1') and not to be changed. The direction of PFS and PDC: input (slave) or output (master) is determined by the Master/Slave strap (DREQR pin) during reset. Data Sheet 233 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.3 CLKOUT Control Register CLKOUT Control Register (CLKOUT) read/write Reset value: 0008H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 CLKOUTEN 10 x 2 9 x 1 CLKOUT 8 x 0 Address: D082H Note: 'x' = unused bits, read as 0 . CLKOUTEN CLKOUT Pin Enable 0= 1= CLKOUT 000 = 001 = 010 = 011 = 100 = CLKOUT pin is in tri-state. CLKOUT pin is active. (default) 2.048 MHz 4.096 MHz (default) 8.192 MHz 15.36 MHz 16.384 MHz CLKOUT Pin Frequency Data Sheet 234 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.4 DCXO Reference Clock Select Register REFSEL Register (CREFSEL) Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 REFSEL EN 10 x 2 9 x 1 REFSEL(2:0) 8 x 0 read/write Address: D083H Note: 'x' = unused bits, read as 0 This register controls the selection of the source of the DCXO 8kHz reference clock REFSELEN DCXO Reference Clock Enable 0= 1= 000 = 001 = 010 = 011 = 100 = 101 = The reference clock is disabled (default) The reference clock is enabled DXCLK/192 (default) XCLK/256 XCLK REFCLK (when input) REFCLK (when input)/64 PFS (when input) REFSEL(2:0) DCXO Reference Clock Select Data Sheet 235 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.5 REFCLK Control Register REFCLK Control Register (CREFCLK) read/write Reset value: 0003H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 REFCLKEN 10 x 2 9 x 1 REFDIV(2:0) 8 x 0 Address: D084H Note: 'x' = unused bits, read as 0. REFCLK may be configured as an input or as an output. When configured as an input, it may be used as a source for the on-chip DCXO 8kHz reference clock. This option is handled by the DCXO Reference Clock Select Register (CREFSEL). When configured as an output it is derived from XCLK input pin. In order to drive REFCLK, XCLK may be divided by 256, 192, 4, 3 or 1. REFCLKEN REFCLK Pin Output Enable 0= 1= REFCLK is input, the pad is not output enabled REFCLK is output REFDIV(2:0) REFCLK Pin Output Divider Selection This determines the value by which the XCLK maximum clock of 2.048 MHz is divided internally. 000 = 001 = 010 = 011 = 100 = Division by 256 Division by 192 Division by 4 Division by 3 (default) Division by 1 Data Sheet 236 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.6 DCL_2000 Control Register DCL_2000 Control Register (CDCL2) read/write Reset value: 0004H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 DCL2EN 9 x 1 8 x 0 Address: D085H DCL2(1:0) Note: 'x' = unused bits, read as 0 . DLC2EN DCL_2000 Clock Enable 0= 1= 00 = 01 = 10 = DCL_2000 clock is disabled DCL_2000 clock is enabled (default) 3.072 MHz (default) 6.144 MHz 12.288 MHz DCL2(1:0) DCL_2000 Clock Rate Data Sheet 237 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.7 DCL Control Register DCL Control Register (CDCL) Reset value: 000BH 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 DCLEN 10 x 2 9 x 1 DCL(2:0) 8 x 0 read/write Address: D086H Note: 'x' = unused bits, read as 0 . DCLEN DCL Clock Enable 0= 1= DCL is disabled DCL is enabled (default) 384 kHz 768 kHz 1536 kHz 2048 kHz (default) 4096 kHz DCL(2:0) DCL Clock Rate 000 = 001 = 010 = 011 = 100 = Data Sheet 238 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.8 FSC Control Register FSC Control Register (2) Reset value: 0002H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 IFSCD 10 x 2 EFSCD 9 x 1 FSCEN 8 x 0 FSCSH read/write Address: D087H Note: 'x' = unused bits, read as 0 . FSCEN FSC Clock Enable 0= 1= FSC is disabled (stuck at '0') FSC is enabled (default) The next FSC pulse will be longer than 2 DCL cycles (default) The next FSC pulse will be shorter than 2 DCL cycles (short FSC) no delay between FSC and DCL rising edge (recommended for VIP V2.1 and higher) FSC rising edge is delayed by one CLK61 clock (16 ns) relative to DCL/ DCL2000 (suitable only for VIP up to V1.1) no delay between FSC and DCL rising edge (default) FSC rising edge is delayed by one CLK61 clock (16 ns) relative to DCL/ DCL2000 (only for test purpose) Note: If only one short FSC pulse is needed, this bit should be reset to '0' by the DELIC software, after the next FSC rising edge detection (after the beginning of the next frame). It is not executed automatically by the hardware. FSCSH Short FSC Pulse 0= 1= EFSCD External FSC Delay 0= 1= IFSCD Internal FSC Delay (only valid if CSTRAP: bit0 = 1) 0= 1= Data Sheet 239 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.9 L1_CLK Control Register L1_CLK Control Register (CL1CLK) Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 x 10 x 2 x 9 x 1 L1CLKDIS 8 x 0 L1CLK read/write Address: D088H Note: 'x' = unused bits, read as 0 . L1CLKEN L1_CLK Disable 0= 1= L1CLK 0= 1= L1_CLK is enabled (default) L1_CLK is disabled 7.68 MHz (default) 15.36 MHz L1_CLK Clock Rate Data Sheet 240 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.10 PFS Sync Register PFS Sync Register (CPFSSY) Reset value: 0000H 15 x 7 x 14 x 6 x 13 x 5 x 12 x 4 x 11 x 3 10 x 2 9 x 1 8 x 0 read/write Address: D089H PFSSYNC(1:0) Note: 'x' = unused bits, read as 0. PFSSYNC has to written once during initialization (value don't care) to bring the rising edge of FSC close to PFS. Note: PFS and FSC are not exactly aligned. See "AC Characteristics" on Page 249 for more information. Data Sheet 241 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.11 Real-time Counter Register RT Counter Register (CRTCNT) Reset value: 0000H 15 14 13 12 11 10 9 8 read Address: D08EH RTCOUNT(15:8) 7 6 5 4 3 2 1 0 RTCOUNT(7:0) This 18-bit counter counts 8 kHz cycles. It is used by the software to time the handling of required tasks. One period of the counter (counting from 0000H to FFFFH and back to 0000H) is 32.768 sec. Only the 16 MSBs of the counter may be read by the OAK, therefore the actual resolution is 0.5 ms.. RTCOUNT(15:0) The 16 MSBs of the real-time counter Data Sheet 242 2003-07-31 PEB 20570 PEB 20571 Register Description 6.2.11.12 Strap Status Register Strap Status Register (CSTRAP) Reset value: 0000 0xxx xxxx xx10B 15 x 7 14 x 6 13 x 5 12 x 4 11 x 3 2 10 9 STRAP(10:8) 1 0 8 read/ write Address: D08FH STRAP(7:0) Note: 'x' = unused bits, read as 0 Note: . STRAP (10:0) This register enables the OAK to read the straps values, as sampled during reset bit 10 bit 9:7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 PCM Clock Master Strap Test Mode Strap Emulation Boot Strap PLL Bypass Strap DSP PLL Power-Down Strap Boot Strap Reset counter Bypass Strap DCXO Fast-Synchronization Enable (read/write) 0= 1= bit 0 0= 1= Linear (slow) synchronization (for DECT applications) Fast synchronization (default) PFS, PDC, DCL, FSC, DCL2000 are delayed by some ns (default) PFS, PDC, DCL, FSC, DCL2000 are not delayed Internal Source Clock Strap (read/ write) Data Sheet 243 2003-07-31 PEB 20570 PEB 20571 Package Outlines 7 Package Outlines P-TQFP-100-3 (Plastic Thin Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 244 Dimensions in mm 2003-07-31 GPM05247 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8 8.1 Parameter Electrical Characteristics and Timing Diagrams Absolute Maximum Ratings Symbol Limit Values - 65 to 150 - 0.3 to 4.6 - 0.3 to 6.0 - 0.3 to VDD + 0.3 - 0.3 to 6.0 Unit C V V V V V Storage temperature IC supply voltage DC input voltage (except I/O) DC output voltage (including I/O); output in high or low state DC output voltage (including I/O); output in tri-state ESD robustness1) HBM: 1.5 k, 100 pF 1) Tstg VDD VI VO VI, VO VESD,HBM 2000 According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993. The Pins (TBD) are not protected against voltage stress > (TDB) V (versus VS or GND). The (TBD) performance prohibits the use of adequate protective structures. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Data Sheet 245 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8.2 Parameter Operating Range Symbol Limit Values min. max. 3.47 V 0V 5.5 V 0 0 0 0 0 0 3.13 Unit Power Supply Voltage Ground Voltage applied to input pins Voltage applied to output or I/O pins outputs enabled outputs high-Z Operating temperature Input transition rise or fall time PEB VDD VSS VIN VOUT VOUT TA t/v VDD V 5.5 V 70 C 10 ns/V Note: In the operating range, the functions given in the circuit description are performed. Data Sheet 246 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8.3 Parameter DC Characteristics Symbol Limit Values min. max. 2.0 - 0.3 2.4 Unit Test Condition V V V VOUT >= VOH (min) VOUT <= VOL (max) High-Level Input Voltage Low-Level Input Voltage VIH VDD + 3.31) 0.8 VIL High-Level Output voltage VOH (all pins except DD0, DD1, DX, LTxD0, TxD0, TxD1) Low-Level Output voltage VOL (all pins except DD0, DD1, DX, LTxD0, TxD0, TxD1) High-Level Output voltage VOH (pins DD0, DD1, DX, LTxD0, TxD0, TxD1) Low-Level Output voltage VOL (pins DD0, DD1, DX, LTxD0, TxD0, TxD1) Input leakage current VDD = min, IOH = - 2 mA VDD = min, IOL = 2 mA VDD = min, IOH = - 7 mA VDD = min, IOL = 7 mA VDD = 3.3 V, GND = 0 V; all other pins are floating; VIN = 0 V VDD = 3.3 V, GND = 0 V; VOUT = 0 V 0.4 V 2.4 V 0.4 V IIL 1 A Output leakage current IOZ 1 A Avg. power supply current IInit ICC (AV) IAP2) 266.5 272.6 275 mA VDD = 3.3 V, TA = 25 C: PDC = 8 MHz DSP @ 61.44 MHz 1) 2) max. value < 5.5 V Power supply current for an application with 6 digital and 2 analogue phones including switching. Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Data Sheet 247 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8.4 Parameter Capacitances Symbol Limit Values min. max. 7 7 10 3.3 3.3 pF pF pF pF pF Unit Notes Input Capacitance I/O Capacitance Output Capacitance Crystal input capacitance (pin CLK16-XI) CIN CI/O COUT CXIN fC = 1 MHz, The pins, which are not under test, are connected to GND Crystal output capacitance CXOUT (pin CLK16-XO) 8.5 Parameter Recommended 16.384 MHz Crystal Parameters Symbol 25 7 15 30 150 Limit Values min. max. fF pF pF ppm Unit Test Condition C1 Shunt Capacitance C0 External Load Capacitance CL Resonance Resistance Rr Motional Capacitance Frequency Calibration Tolerance Data Sheet 248 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8.6 8.6.1 AC Characteristics DMA Access Timing The exact behavior required from every P interface signal during a DMA access, determined according to the following modes: 1. Motorola/Intel Mode: Determined by the MODE input pin. 2. Normal/Fly-By mode: Programmable mode, in the control register of the P-interface. In any mode, the DACK input alone is used to indicate that this is a DMA transaction, and to select the DMA mail-box. An activation of CS is not required in such cases. 8.6.1.1 DMA Access Timing In Motorola Mode In this mode DS is used for timing the access, while R/W is used to distinguish between DMA read transactions and DMA write transactions. The R/W input signal is used differently in Normal mode and in Fly-By mode. The next table details the way in which R/W should be used in each mode, during DMA transactions: Table 63 Mode Normal (Non-Fly-By) R/W Behavior During DMA Transactions in Normal and in Fly-By Mode R/W = `0' Write DMA transaction. (A response to DMA transmitter request) Read DMA transaction. (A response to DMA receiver request) R/W = `1' Read DMA transaction. (A response to DMA receiver request) Write DMA transaction. (A response to DMA transmitter request) Fly-By In Fly-By mode R/W is used inverted, because the same signal, R/W, is required for concurrent accessing of an external memory device. Data Sheet 249 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Table 64 Parameter DACK setup time to DS falling edge DACK hold time after DS rising edge DMA Transaction timing in Motorola Mode Symbol min. tSAS tHSA 7 5 5 8 0 7 5 30 0 0 22 15 36 Limit Values max. ns ns ns ns ns ns ns ns ns ns Unit Test Conditions Output load capacity of 50 pF D-bus setup time to DS rising tSDS edge D-bus hold time after DS rising edge DREQT/DREQR delay after DS falling edge tHSD tDSR R/W setup time to DS falling tSRWS edge R/W hold time after DS rising tHSRW edge DS pulse width and interval between DS pulses D-bus valid after DS falling edge tWS tDSDV D-bus float (high impedance) tDSDT after DS rising edge Data Sheet 250 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams tWS tSRWS tSAS DS DACK tSDS tWS tHSA tHSRW R/W tHSD D DREQT Figure 59 DMA Write-Transaction Timing in Motorola Mode last byte tDSR Note: R/W is described in Normal mode. In Fly-by mode, R/W should be high during DMA write transactions. Data Sheet 251 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams tWS tSRWS tSAS DS DACK tWS tHSA tHSRW R/W tDSDT tDSDV D DREQR Figure 60 DMA Read-Transaction Timing in Motorola Mode last byte tDSR Note: R/W is described in Normal mode. In Fly-by mode, R/W should be low during DMA read transactions. 8.6.1.2 DMA Access Timing In Intel/Infineon Mode In this mode R and W are used for timing the access and to determine whether it's a DMA-read cycle or DMA-write cycle. R and W input signals are used in opposite ways in Normal mode and in Fly-By mode. The next table details the way in which R and W should be used in each mode, during DMA transactions: Data Sheet 252 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Table 65 Mode Normal (Non-Fly-By) R/W Behavior During DMA Transactions in Normal and in Fly-By Modes R = `1', W = `0' Write DMA transaction. (A response to DMA transmitter request) Read DMA transaction. (A response to DMA receiver request) R = `0', W = `1' Read DMA transaction. (A response to DMA receiver request) Write DMA transaction. (A response to DMA transmitter request) Fly-By In Fly-By mode R and W are used inverted, because these signals are required also for concurrent accessing of an external memory device. Table 66 Parameter DACK setup time to W or R falling edge DMA Transaction Timing in Intel/Infineon Mode Symbol min. tSAW tSAR 7 5 5 8 0 30 30 0 0 22 15 36 Limit Values max. ns ns ns ns ns ns ns Unit Test Conditions Output load capacity of 50 pF DACK hold time after W or R tHWA rising edge tHRA D-bus setup time to W rising tSDW edge D-bus hold time after W rising edge DREQT/DREQR delay after W or R falling edge W pulse width and interval between W pulses R pulse width and interval between R pulses D-bus valid after R falling edge tHWD tDWR tDRR tWW tWR tDRDV D-bus float (high impedance) tDRDT after R rising edge Data Sheet 253 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams tWW tSDW tSAW WR(RD) DACK tWW tHWA tHWD D DREQT Figure 61 DMA Write-Transaction Timing in Intel/Infineon Mode Note: The figure describes a transaction in Normal mode. In Fly-by mode, RD is used during DMA write transactions, instead of WR. last byte tDWR tWR tSAR RD(WR) DACK tWR tHRA tDRDT tDRDV D DREQR Figure 62 DMA Read-Transaction Timing in Intel/Infineon Mode Note: The figure describes a transaction in Normal mode. In Fly-by mode, WR is used during DMA read-transactions, instead of RD. last byte tDRR Data Sheet 254 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8.6.2 P Access Timing P accesses DELIC by an activation of Address and CS. 1. By driving the MODE pin `high' the user chooses Motorola Work Mode, by driving it `low' - Intel/Infineon Work Mode. The pin is sampled by RESET rising edge. 2. Moreover, there is a difference between work with Multiplexed Address/Data Bus and Demultiplexed Address and Data Buses (in Intel/Infineon Mode). In Motorola Mode Demultiplexed Buses only used. The selection between Multiplexed and Demultiplexed is done by the manner of use of ALE. 8.6.2.1 P Access Timing in Motorola mode In this mode R/W distinguishes between Read and Write interactions, and DS is used for timing. Table 67 Parameter Timing for Write Cycle in Motorola Mode Symbol Limit Values min. R/W setup time before DS x CS rising tSRWS edge R/W hold time after DS x CS rising edge A-bus setup time before DS x CS rising edge A-bus hold time after DS x CS rising edge D-bus setup time before DS x CS rising edge D-bus hold time after DS x CS rising edge DS X CS pulse width tHRWS tSAS tHAS tSDS tHDS tWS 17 5 22 6 5 8 17 max. ns ns ns ns ns ns ns Output load capacity of 50 pF Unit Notes Note: DS X CS is active (low) when both, DS and CS, are active (low) Data Sheet 255 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams tSRWS R/W tSAS A tSDS D tWS DS x CS Figure 63 Table 68 Parameter R/W setup time before DS X CS falling edge R/W hold time after DS X CS rising edge A-bus valid to D-bus valid DS X CS falling edge to D-bus Write Cycle Motorola Mode tHRWS tHAS tHDS Timing for Read Cycle In Motorola Mode Symbol tSRWS tHRWS tDAD tDSD Limit Values min. 0 5 0 0 0 28 28 16 max. ns ns ns ns ns Output load capacity of 50 pF Unit Notes D-bus float after DS X CS rising edge tDSDH Note: DS X CS is active (low) when both, DS and CS are active (low) Data Sheet 256 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams A tSRWS R/W DSxCS tDAD tDSD D Figure 64 Read Cycle Motorola Mode tHSRW tDSDH 8.6.2.2 P Access Timing in Intel/Infineon Mode In this mode driving RD `low' causes Read access, driving WR `low' causes Write access. In order to work on demultiplexed bus ALE has to be driven `high' all the time. Table 69 Parameter A-bus setup time before WR rising edge Timing for Write Cycle in Intel/Infineon Demultiplexed Mode Symbol tSAW Limit Values min. 12 5 12 5 6 8 7 max. ns ns ns ns ns ns ns Output load capacity of 50 pF Unit Notes A-bus hold time after WR rising edge tHAW CS setup time before WR rising edge tSCW CS hold time after WR rising edge D-bus setup time before WR rising edge WR pulse width tHCW tSDW D-bus hold time after WR rising edge tHDW tWW Data Sheet 257 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams tWW tSCW tSAW tSDW WR A CS D tHCW tHAW tHDW Figure 65 Write Cycle Intel/Infineon Demultiplexed Mode Table 70 Parameter Timing For Read Cycle in Intel/Infineon Demultiplexed Mode Symbol tDAD tDRD Limit Values min. max. 28 28 16 ns ns ns Output load capacity of 50 pF 0 0 0 Unit Notes A-bus valid to D-bus valid RD X CS falling edge to D-bus D-bus float after RD X CS rising edge tDRDH Note: RD X CS is active (low) when both, RD and CS are active (low) A RDxCS tDAD tDRD D Figure 66 Read Cycle Intel/Infineon Demultiplexed Mode tDRDH Data Sheet 258 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Timing for Multiplexed Bus In this mode ALE pin is used in order to lock the address, driven over the multiplexed A/D bus. Table 71 Parameter A-bus setup time before ALE falling edge ALE pulse width CS hold time after WR rising edge D-bus setup time before WR rising edge ALE hold time after WR rising edge WR pulse width Timing for Write Cycle in Intel/Infineon Multiplexed Mode Symbol tSAL Limit Values min. 12 5 7 14 5 6 8 5 7 max. ns ns ns ns ns ns ns ns ns Output load capacity of 50 pF Unit Notes A-bus hold time after ALE falling edge tHAL tWL tHCW tSDW CS setup time before WR rising edge tSCW D-bus hold time after WR rising edge tHDW tHLW tWW tWW WR tSCW CS tSAL AD tWL ALE Figure 67 Write Cycle Intel/Infineon Multiplexed Mode Address tHCW tHDW Data tHAL tSDW tHLW Data Sheet 259 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Table 72 Parameter Timing For Read Cycle in Intel/Infineon Multiplexed Mode Symbol Limit Values min. ALE low before RD X CS falling edge tHRL ALE hold time after RD X CS rising edge ALE pulse width A-bus setup time before ALE falling edge RD X CS falling edge to D-bus valid tHLR tWL tSAL 5 5 7 12 5 0 0 28 16 max. ns ns ns ns ns ns ns Output load capacity of 50 pF Unit Notes A-bus hold time after ALE falling edge tHAL tDRD D-bus float after RD X CS rising edge tDRDH tHRL RDxCS tWL ALE tSAL AD Figure 68 tHLR tHAL tDRD Data tDRDH Address Read Cycle in Intel/Infineon Multiplexed Mode 8.6.3 Interrupt Acknowledge Cycle Timing The IREQ (Interrupt REQuest) output signal of the DELIC is activated as a result of a DSP writing operation to the OCMD register (OAK mailbox command register). Such an operation sets the OAK mailbox busy bit (OBUSY), which drives directly the IREQ output signal. The IREQ signal may be masked, by programming the MASK bit within the Pinterface Control Register (UPCR). The P may force the DELIC to drive the interrupt-vector over the data-bus, by activation (low) of the interrupt acknowledge input signal (IACK). In Motorola mode an interrupt acknowledge cycle consists of one IACK pulse, during which the interrupt vector is issued by the DELIC. In Intel/Infineon mode an interrupt acknowledge cycle consists of Data Sheet 260 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams two IACK pulses, and the interrupt vector is issued as a response to the second one. The vector's source the OAK mailbox vector register (OVEC). The value stored in this register is determined by the OAK, by writing operation. IREQ is not deactivated by the IACK pulses directly, but by P writing access to OBUSY. Table 73 Parameter D-bus valid after IACK falling edge D-bus float after IACK rising edge IACK pulse width Interval between two IACK pulses IREQ delay after WR or DS 1) Interrupt Acknowledge Cycle Timing Symbol tDADV tDADT tWA tHA tDWI Limit Values min. 0 0 25 101) 28 max. 31 19 ns ns ns ns ns Output load capacity of 50 pF Unit Notes Valid only for Intel/Infineon mode. IACK tDADT tDADV D Figure 69 vector Interrupt Acknowledge Cycle Timing in Motorola Mode tWA IACK tHA tWA tDADT tDADV D Figure 70 vector Interrupt Acknowledge Cycle Timing in Intel/Infineon Mode Data Sheet 261 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams DSxCS WR IREQ Figure 71 IREQ Deactivation Timing tDWI Note: IREQ is deactivated due to P write operation to OBUSY register. In Motorola mode DS and CS together time the write access. In Intel mode WR alone times the write access. For more details regarding the timing required during write access to the DELIC, refer to section 8.6.2. The other signals required for a write operation to OBUSY in each mode, are assumed to be driven appropriately. 8.6.4 Table 74 Parameter IOM-2 Interface Timing IOM-2 Interface Timing Symbol 10 10 10 10 7 6 27 22 Limit Values min. typ. max. ns ns ns ns ns ns Output load capacity of 50 pF Unit Notes DU0/DU1 setup time before tUDF DCL falling edge DU0/DU1 hold time after DCL falling edge DRDY setup time before DCL falling edge1) DRDY hold time after DCL falling edge DD0/DD1 delay after DCL rising edge DD0/DD1 float after DCL rising edge 1) tUHF tYDF tYHE tDDE tDFE DRDY is sampled only once during every IOM-2 channel, with the first D-bit (D0). For more details refer to "Support of DRDY Signal from QUAT-S" on Page 103 Note: FSC and DCL are outputs of the DELIC. Yet, DCL is used also in the DELIC for sampling and driving of the other signals of the IOM-2 interface, and thus the timing of these signals is related to DCL. Data Sheet 262 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams DCL FSC tDDE tDFE Single Data Rate Mode DD0/DD1 tUDF tUHF DU0/DU1 Double Data Rate Mode tDDE tDFE DD0/DD1 tUDF tUHF DU0/DU1 Figure 72 IOM-2 Interface Timing Single Data-Rate DCL Double Data-Rate DCL tYDF tYHE DU0 DRDY Figure 73 DRDY Timing 1st bit tYDF 2nd bit tYHE Data Sheet 263 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Table 75 Parameter DCL Clock Period DCL (IOM-2 Data Clock) Timing Symbol tDCP Limit Values min. typ. 2.604 1.302 651 488 244 DCL Duty Cycle 48 50 52 max. s s ns ns ns % DCL = 384 kHz DCL = 768 kHz DCL = 1536 kHz DCL = 2048 kHz DCL = 4096 kHz Unit Notes Note: Usually DSP-clock is generated internally by the internal PLL, in a frequency of 61.44 MHz. If on the other hand a lower frequency clcok is provided via CLK_DSP input pin, the frequency of DCL should not exceed the frequency of DSP-clockfrequency / 4 (DSP clcok frequency devided by 4), in order to guarantee a proper operation of the DELIC. tDCP DCL Figure 74 Table 76 Parameter DCL Timing IOM-2 FSC (IOM-2 and IOM-2000 Frame-Sync) Timing Symbo Limit Values Unit Notes l min. typ. max. -10 10 ns Output load capacity of up to 50 pF on both, PFS and DCL 8 kHz FSC delay after DCL rising tFDE edge1) FSC Clock Period tFSC 125 112 112.5 113 s s FSC Clock Period High in a tHLC long-pulse FSC cycle2) Data Sheet 264 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Table 76 Parameter FSC (IOM-2 and IOM-2000 Frame-Sync) Timing (cont'd) Symbo Limit Values Unit Notes l min. typ. max. 2.5 1.2 640 480 235 1) FSC Clock Period High in a tHSC short-pulse FSC cycle3) 2.604 2.7 1.302 1.4 651 488 244 660 490 255 s s ns ns ns DCL = 384 kHz DCL = 768 kHz DCL = 1536 kHz DCL = 2048 kHz DCL = 4096 kHz FSC rises and falls by DCL rising edge, and should be sampled with the falling edge of DCL, in the other chips, connected to the IOM-2 interface of the DELIC. In a long-pulse FSC cycle, FSC is generated with a 50% duty cycle. FSC Clock Period Low is the complement of this parameter to 125 s. In a short-pulse FSC cycle, FSC is high for exactly one cycle of DCL, thus it is dependent on the frequency of DCL. FSC Clock Period Low is the complement of this parameter to 125 s. 2) 3) DCL tFDE tFDE tFSC tHLC FSC Long-Pulse tFDE tHSC tFDE FSC Short-Pulse tFSC Figure 75 FSC Timing IOM-2 Data Sheet 265 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8.6.5 Table 77 Parameter PCM Interface Timing PCM Interface Timing Symb ol tRPF tRHF Limit Values min. 10 10 10 10 10 10 25 -10 125 48 tTPF tTFR tTDR 2 2 2 50 52 19 20 19 10 typ. max. ns ns ns ns ns ns ns ns s % ns ns ns In master mode, when PFS and PDC are outputs. TxD0..3 In slave mode, when PFS and PDC are inputs. Unit Notes RxD0..3 setup time before PDC falling edge RxD0..3 hold time after PDC falling edge PFS setup time before PDC tPSP falling edge1) PFS setup time before PDC tPPR rising edge2) PFS hold time after PDC falling edge1) PFS hold time after PDC rising edge2) PFS Pulse Width (high)3) PFS delay after PFS Duty Cycle TxD0..3 delay after PDC rising edge TxD0..3 float after PDC rising edge TSC0..3 delay after PDC rising edge 1) tHPF tHPR tPPW tPDP tPCP PDC4) PFS Clock Period In 8 kHz PFS - slave mode, PFS is sampled by PDC falling edge. The first PDC cycle in which FSC is sampled as logic-1 after a sampling of logic-0, is considered as the first cycle of the new PCM frame. Also see "PCM Master/Slave Mode Clocks Selection" on Page 144 In 4 kHz PFS - slave mode, PFS is sampled by PDC rising edge. In order to work appropriately in this mode, PFS should be sampled as logic-1 only once every frame. The cycle in which PFS is sampled as logic-1 is considered as the first cycle of the new frame. Also see "PCM Master/Slave Mode Clocks Selection" on Page 144 Inside the DELIC, PFS is also sampled by DSP-clock (61.44 MHz). Since this clock (DSP-clock) is not visible for the user, a pulse width of more then one 61.44 MHz cycle is required, in order to guarantee an appropriate sampling. 2) 3) Data Sheet 266 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 4) In PCM Master mode (PFS and PDC are in output mode) PFS rises with a rising edge of PDC, and it's designed to be sampled with the falling edge of PDC at any (slave) chip connected to the PCM interface. The first PDC cycle in which PFS is sampled as logic-1 after a sampling of logic-0, is considered as the first cycle of the new PCM frame. PDC tPSP tHPF tPPW PFS(8 KHz) tPPR tHPR tPPW PFS(4 KHz) Figure 76 PFS Timing in Slave Mode (Input PCM Clocks) PDC tPDP tPDP tPCP PFS(8 KHz) Figure 77 PFS Timing in Master Mode Data Sheet 267 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams PDC tTDR tTDR TSC0..3 tTPF tTFR Single Data Rate Mode TXD0..3 tRPF tRHF RXD0..3 tTPF tTFR Double Data Rate Mode TXD0..3 tRPF tRHF RXD0..3 Figure 78 PFS Interface Timing Table 78 Parameter PDC Clock Period PDC (PCM Data Clock) Timing in Master Mode (Output Mode) Symbol tPCP Limit Values min. typ. 488 244 122 61 max. ns ns ns ns 52 % PDC = 2048 kHz PDC = 4096 kHz PDC = 8192 kHz PDC = 16384 kHz Unit Notes PDC Duty Cycle tPDC 48 Data Sheet 268 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Note: Usually DSP-clock is generated internally by the internal PLL, in a frequency of 61.44 MHz. If on the other hand a lower frequency clcok is provided via CLK_DSP input pin, the frequency of PDC (input or output) should not exceed the frequency of DSP-clock-frequency / 4 (DSP clcok frequency devided by 4), in order to guarantee a proper operation of the DELIC. tPCP PDC Figure 79 Table 79 Parameter PDC Minimum High Pulse PDC Minimum Low Pulse PDC Parameters PDC Timing in Input Mode Symbol tPMH tPML 22 22 Limit Values min. typ. max. ns ns In Input Mode In Input Mode Unit Notes Note: The Minimum pulse width (high or low) of PDC depends on the DSP clock frequency. Usually this clock is generated internally by the internal PLL, in a frequency of 61.44 MHz. In this case the values in the table above are valid. If a lower frequency for DSP-clock is provided via CLK_DSP input pin, and PDC is used as input, the low/high pulse width of PDC should not be smaller then 1.5 X DSP-clock-cycle (DSP-clock-cycle is the cycle time of the provided DSP clock). tPML tPMH PDC Figure 80 PDC Timing in Input Mode Data Sheet 269 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8.6.6 Table 80 Parameter IOM-2000 Interface Timing IOM-2000 Interface Timing Symbo Limit Values Unit Notes l min. typ. max. tDSF tDHF 1 12 20 1 12 20 -10 6 10 26 ns ns ns ns ns ns ns ns CFSC:EFSCD = `0' 2) CFSC:EFSCD = `1'3) DR setup time before DCL_2000 falling edge DR hold time after DCL_2000 falling edge DX delay after DCL_2000 tXDR rising edge STAT setup time before DCL_2000 falling edge STAT hold time after DCL_2000 falling edge CMD delay after DCL_2000 rising edge FSC rising edge delay after DCL_2000 rising edge1) (In both, long and short pulse FSC cycles) FSC falling edge delay after DCL_2000 rising edge FSC falling edge delay after DCL_2000 falling edge 4) FSC Clock Period 1) tSSF tSHF tCDR tFRE tFFE -10 26 ns Long-pulse FSC cycle tFFF 70 ns Short-pulse FSC cycle DCL_2000 = 3072 kHz DCL = 4096 kHz tFCD 125 s FSC is the same pin used for the IOM-2 interface (Table 76). FSC rises with a rising edge of DCL_2000, and it's designed to be sampled with the falling edge of DCL_2000 at any chip connected to the IOM-2000 interface. The first DCL-2000 cycle in which FSC is sampled as logic-1 after a sampling of logic-0, is considered as the first cycle of the new IOM-2000 frame. When a long-pulse FSC cycle is issued, FSC always rises and falls with a rising edge of DCL_2000, and it is generated with a 50% duty cycle. FSC Control Register : EFSCD (bit 2) = `0', i.e. no delay between DCL_2000 rising edge and FSC rising edge. "FSC Control Register" on Page 239 2) Data Sheet 270 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 3) FSC Control Register : EFSCD (bit 2) = `1', i.e. FSC rising edge is delayed in one cycle of 61.44 MHz (16 ns) after DCL_2000 rising edge. Special mode designed for working with the VIP. "FSC Control Register" on Page 239 When a short-pulse FSC cycle is issued, FSC high period is one DCL (of IOM-2) cycle long. In the worst case, when DCL_2000 = 3072 kHz and DCL = 4096 kHz, FSC high pulse is shorter than one cycle of DCL_2000, but yet it is stable from the rising edge and until at least 70 ns after the falling edge of DCl_2000 within this single cycle. Thus setup and hold times of FSC around DCL_2000's falling edge are guaranteed. 4) FSC DCL_2000 tXDR tXDR DX tDSF ch0 tDHF ch1 ch2 ch3 DR ch2 tCDR ch3 ch4 ch5 CMD tSSF tSHF STAT Figure 81 IOM-2000 Interface Timing Data Sheet 271 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams DCL_2000 tFCD tFRE tFFE FSC tFFF tFRE FSC-Short tFCD Figure 82 Table 81 Parameter DCL_2000 Clock Period FSC Timing IOM-2000 DCL_2000 (IOM-2000 Data Clock) Timing Symbo Limit Values Unit Notes l min. typ. max. tDCP 325 162 81 DCL_2000 Duty Cycle tDDC 48 52 ns ns ns % DCL_2000 = 3072 kHz DCL_2000 = 6144 kHz DCL_2000 = 12288 kHz Note: Usually DSP-clock is generated internally by the internal PLL, in a frequency of 61.44 MHz. If on the other hand a lower frequency clcok is provided via CLK_DSP input pin, the selected frequency of DCL_2000 should not exceed the frequency of DSP-clock-frequency / 4 (DSP clcok frequency devided by 4), in order to guarantee a proper operation of the DELIC. Data Sheet 272 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8.6.7 Table 82 Parameter LNC0..3 (Local Network Controller) Interface Timing LNC0..3 Interface Timing Symb ol Limit Values min. 10 14 10 10 24 20 23 typ. max. ns ns ns ns ns ns ns LTxD0..3 Unit Notes LRXD0..3 setup time before tLSL LCLK0..3 falling/rising edge LRXD0..3 hold time after tLHL LCLK0..3 falling/rising edge LCxD0..3 setup time before tCSL LCLK0..3 falling/rising edge LCxD0..3 hold time after tCHL LCLK0..3 falling/rising edge LTxD0..3 delay after LCLK0..3 rising edge LTxD0..3 float after LCLK0..3 rising edge LTSC0..3 delay after LCLK0..3 rising edge tTDR tTFR tSCR Data Sheet 273 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams LCLK0..3 tSCR LTSC0..3 tTDR tTFR LTXD0..3 tLSL tLHL Sampling with rising edge LRXD0..3 tCSL tCHL LCXD0..3 tLSL tLHL Sampling with falling edge LRXD0..3 tCSL tCHL LCXD0..3 Figure 83 LNC0..3 (Local Network Controller) Interface Timing Data Sheet 274 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Table 83 Parameter LCLK0..3 Clock Period LCLK0..3 Timing in Output Mode Symb ol tLCP Limit Values min. typ. 488 244 122 61 LCLK0..3 Duty Cycle in output mode 48 52 max. ns ns ns ns % LCLK0..3 = 2048 kHz LCLK0..3 = 4096 kHz LCLK0..3 = 8192 kHz LCLK0..3 = 16384 kH z Unit Notes Note: LCLK0..3 are generated with a 50% duty cycle. Even though all LCLKs (0, 1, 2, 3) might be operated in all possible frequencies, the frequency of each one of these clocks should be configured in accordance with the GHDLCU operating mode. For more detailes see section 6.2.6.2 "GHDLC Channel Mode Register". Usually DSPclock is generated internally by the internal PLL, in a frequency of 61.44 MHz. If on the other hand a lower frequency clcok is provided via CLK_DSP input pin, the frequency of LCLK0..3 (input or output) should not exceed the frequency of DSPclock-frequency / 4 (DSP clcok frequency devided by 4), in order to guarantee a proper operation of the DELIC. tLCP LCLK0..3 Figure 84 Table 84 Parameter LCLK0..3 Minimum High Pulse LCLK0..3 Minimum Low Pulse LCLK0..3 Timing in Output Mode LCLK0..3 Timing in Input Mode Symbo Limit Values Unit Notes l min. typ. max. tLMH tLML 22 22 ns ns In Input Mode In Input Mode Data Sheet 275 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Note: The frequency of each LCLKn pin (n = 0,1,2,3) should not exceed the maximum frequency, defined according to the GHDLCU operating mode. For more detailes see section 6.2.6.2 "GHDLC Channel Mode Register". The Minimum pulse width (high or low) of LCLK0..3 depends on the DSP clock frequency. Usually this clock is generated internally by the internal PLL, in a frequency of 61.44 MHz. In this case the values in the table above are valid. If a lower frequency for DSP-clock is provided via CLK_DSP input pin, and PDC is used as input, the low/high pulse width of PDC should not be smaller then 1.5 X DSP-clock-cycle (DSP-clock-cycle is the cycle time of the provided DSP clock). Usually DSP-clock is generated internally by the internal PLL, in a frequency of 61.44 MHz. If on the other hand a lower frequency clcok is provided via CLK_DSP input pin, the frequency of LCLK0..3 (input or output) should not exceed the frequency of DSP-clockfrequency / 4 (DSP clcok frequency devided by 4), in order to guarantee a proper operation of the DELIC. tLML tLMH LCLK0..3 Figure 85 Table 85 Parameter CLK_DSP Maximum Frequency CLK_DSP Duty-Cycle LCLK0..3 Timing in Input Mode CLK_DSP Input Clock Timing Symbol tCMF tCDD 48 Limit Values min. typ. max. 61.44 MHz 52 % Unit Notes Note: Usually CLK_DSP is not used. If it is, special care should be taken regarding it's duty-cycle. The duty-cycle of CLK_DSP should be very close to 50%, since this clock is also used for the clock-generation for the OAK (phi1, phi2). Data Sheet 276 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams 8.6.8 Table 86 Parameter JTAG and Emulation Interface Timing Test Interface Timing Symbol tTCJ tCJL tCJH tSUJ tHJR tDSE tDHE tODF tOPD tIPJ tIAJ 30 30 Limit Values min. typ. max. ns ns ns ns ns ns ns 60 60 ns ns ns ns In Update-DR TAP Controller State In Capture-DR TAP Controller State 160 80 80 30 30 30 30 Unit Notes Test Clock (JTCK) Period Test Clock (JTCK) Period Low Test Clock (JTCK) Period High TMS Set-up time before JTCK Rising Edge TMS Hold time after JTCK Rising Edge TDI Set-up time before JTCK Rising Edge TDI Hold time after JTCK Rising Edge TDO Delay after JTCK Falling Edge Any output pin Delay after JTCK Falling Edge Any input pin setup time before JTCK rising edge Any input pin hold time before JTCK rising edge Data Sheet 277 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams tTCJ tCJH tCJL TCK tSUJ tHJR TMS tDSE tDHE TDI tODF TD0 tIPJ tIAJ Any_input tOPD Any_output Figure 86 Table 87 Parameter RESET pulse width RESIND pulse width RESIND deactivation after RESET deactivation Test-Interface (Boundary Scan) Timing Reset and RESIND (Reset Indication) timing Symbo Limit Values Unit Notes l min. typ. max. tRPW tRIW tRDR 430 500 800 800 ns s s Data Sheet 278 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams tRPW RESET tRDR RESIND tRIW Figure 87 Table 88 Parameter Reset Indication Timing CLOCKOUT Timing Symbol tCKP Limit Values min. typ. 488 244 122 65 61 max. ns ns ns ns ns 52 CLKOUT = 2048 kHz CLKOUT = 4096 kHz CLKOUT = 8192 kHz CLKOUT = 15360 kHz CLKOUT = 16384 kHz Unit Notes CLKOUT Period CLKOUT Duty-Cycle 48 50 tCKP CLKOUT Figure 88 Table 89 Parameter L1_CLK Period L1_CLK Duty-Cycle CLOCKOUT Timing L1_CLK Timing Symbol tLCP 48 Limit Values min. typ. 65 130 50 52 max. ns ns % L1_CLK = 15.36 MHz L1_CLK = 7.68 MHz Unit Notes Data Sheet 279 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams tLCP L1_CLK Figure 89 Table 90 Parameter XCLK Period1) L1_CLK Timing XCLK Timing Symbol tXLP Limit Values min. typ. 488 651 125 XCLK Minimum High Period XCLK Minimum Low Period 1) Unit Notes ns ns s ns ns XCLK = 2.048 MHz XCLK = 1.536 MHz XCLK = 8 kHz max. tXLH tXLL 50 50 XCLK is always an input. The frequencies, which are specified in the table above, should be provided by the user. When XCLK is used as a reference clock for the internal DCXO-PLL, one of these specified frequencies must be used, to guarantee proper work of the DELIC. tXLP tXLH tXLL XCLK Figure 90 XCLK Timing Data Sheet 280 2003-07-31 PEB 20570 PEB 20571 Electrical Characteristics and Timing Diagrams Table 91 Parameter REFCLK Period1) REFCLK Timing Symbol tRFP 50 50 Limit Values min. typ. 1.953 125 REFCLK Minimum High tRFH Period REFCLK Minimum Low Period 1) Unit Notes s s ns ns REFCLK = 512 kHz REFCLK = 8 kHz max. tRFL REFCLK may be used either as an input or as an output. When used as an input, the frequencies, which are specified in the table above, should be provided by the user. When REFCLK is used as a reference clock for the internal DCXO-PLL, one of these specified frequencies must be used, to guarantee proper work of the DELIC. tRFP tRFH tRFL REFCLK Figure 91 REFCLK Timing Data Sheet 281 2003-07-31 PEB 20570 PEB 20571 Application Hints 9 9.1 Application Hints DELIC Connection to External Microprocessors CSn WR RD INTR ALE CS WR RD IREQ DRQ0 DRQ1 DACK0 DACK1 DREQR DREQT DACK BLE A(5..1) A0 A(5..1) D(7..0) AD(7..0) 80386EX Vcc 2.7V-3.6V,25MHz DELIC 80386EX.vsd Figure 92 DELIC Connection to Intel 80386EX (Demuxed Configuration) Data Sheet 282 2003-07-31 PEB 20570 PEB 20571 Application Hints DMA Controller HOLD HOLD 8237 8237 HLDA HLDA DRQ0 DRQ1 DREQR DREQT DACK DACK0 DACK1 ALE CSn WR RD INTn CS WR RD IREQ A(5..0) A(5..0) AD(7..0) D(7..0) Infineon C16x 20MHz DELIC C165.vsd Figure 93 DELIC Connection to Infineon C165 (Demuxed Configuration) Data Sheet 283 2003-07-31 9.2 15 PDPR Address: 0xd072 0 00000000 PCMU Data Buffer 0xA000 Figure 94 Data Sheet IN 0 0xA01F 0xA020 RxD0 IN 1 0xA03F 0xA040 RxD1 IN 2 0xA05F 0xA060 RxD2 IN 3 0xA07F 0xA080 RxD3 DELIC Worksheets DSP OUT 0 0xA09F 0xA0A0 TxD0 OUT 1 0xA0BF 0xA0C0 TxD1 DELIC-LC PCM Unit Mode 0 (4 Ports with 2 MBit/s) OUT 2 0xA0DF 0xA0E0 TxD2 284 OUT 3 0xA0FF 15 0 15 TxD3 0 PTSCR0 Address: 0xd062 set and read 0xd063 reset and read PTSCR1 Address: 0xd064 set and read 0xd065 reset and read TSC0 15 15 0 0 15 0 PCR PTSCR2 Address: 0xd066 set and read 0xd067 reset and read Address: 0xd060 DR PTSCR3 Address: 0xd068 set and read 0xd069 reset and read TSC1 15 0 15 0 PTSCR4 Address: 0xd06a set and read 0xd06b reset and read PTSCR5 Address: 0xd06c set and read 0xd06d reset and read TSC2 15 0 15 0 00: 01: 10: 11: DC 0: 1: OD 0: 1: A 0: 1: ICDB 0: 1: SFH 0: 1: 4 x 2.048 Mbit/s 2 x 4.096 Mbit/s 1 x 8.192 Mbit/s 1 x 16.384 Mbit/s single clock double clock push pull mode open drain mode PCMU is idle PCMU is active frame buffer 0 accessed by the DSP frame buffer 1 accessed by the DSP the first 128 time-slots are used the second 128 time-slots are used PTSCR6 Address: 0xd06e set and read 0xd06f reset and read PTSCR7 Address: 0xd070 set and read 0xd071 reset and read Application Hints PEB 20570 PEB 20571 2003-07-31 TSC3 Mailbox-Synchr. 0xD140 (8 Bit) 0xD141 (Inh. bel.) Mailbox-Synchr. Figure 95 Data Sheet P DSP 0x61 (8 Bit) 0xD161 (16 Bit) (Inh. Bel.) Bit 15 OBUSY (P -> DSP) 0x40 MCMD (P -> DSP) 0x41 Bit 7 MBUSY (P <- DSP) P DSP DSP Mailbox OGEN 0xD164 (All) 0xD120 0xD122 0xD124 0xD126 0xD128 0xD12A 0xD12C 0xD163 (MSB) 0xD162 (LSB) 0x63 0x62 0x21 0x20 0x60 OCMD (P <- DSP) 0xD160 (8 Bit) P Mailbox 0xD144 (All) 0xD100 0xD102 0xD104 0xD106 0xD108 0xD10A 0xD10C 0xD10E 0xD143 (MSB) 0xD142 (LSB) 0x43 0x42 MGEN 0x01 0x00 MDT0 0x23 0x22 ODT0 ODT1 ODT2 ODT3 ODT4 ODT5 ODT6 ODT7 0x03 0x02 MDT1 MDT2 0x05 0x04 0x07 0x06 MDT3 0x29 0x28 0x2B 0x2A 0x2D 0x2C 0x2F 0x2E 0x25 0x24 0x27 0x26 0x09 0x08 MDT4 0x0B 0x0A MDT5 Command/ Indication Handshake of General Mailbox 0xD12E 285 0xD110 0xD112 0xD114 0xD116 0xD118 0xD11A 0xD11C 0xD11E 0x0D 0x0C MDT6 0x0F 0x0E MDT7 P Expanded Mailbox 0x31 0x30 0x33 0x32 DSP Expanded Mailbox ODT8 ODT9 ODT10 ODT11 0x39 0x38 0x3B 0x3A 0x3D 0x3C 0x3F 0x3E 0xD130 0xD132 0xD134 0xD136 0x11 0x10 MDT8 0x13 0x12 MDT9 MDT10 0x15 0x14 0x17 0x16 MDT11 0x35 0x34 0x37 0x36 0x19 0x18 MDT12 ODT12 ODT13 ODT14 ODT15 0xD138 0xD13A 0xD13C 0xD13E 0x1B 0x1A MDT13 0x1D 0x1C MDT14 Application Hints PEB 20570 PEB 20571 2003-07-31 0x1F 0x1E MDT15 PEB 20570 PEB 20571 Application Hints 9.3 PCM Output Driver Anomaly When applying the PCM outputs in a bus configuration with pull-ups to 5 V the output drivers of the DELIC have an irregular behavior. As can be seen from the illustration below, the PCM output drivers TXDn (n=0..3) continue to drive 'High' level even outside the time slot enabled by TSC. This error occurs only if the last bit in the time slot is a '1'. In this case no problem occurs if another PCM port drives a '0' in the neighbor time slot. In other words this means that the output driver drives 3.3 V for a certain time against the 5 V pull-up. As soon as a neighbor time slot is driven to '0' by another port the DELIC stops driving immediately. As the occurring current is no problem for the DELIC, this behavior is uncritical. 3.3 V TSC 0V 5V 3.3 V TXD 0V Figure 96 Behavior of Output Driver if Last Bit is '1' 3.3 V TSC 0V 5V 3.3 V TXD 0V Figure 97 Behavior of Output Driver if Last Bit is '0' Data Sheet 286 2003-07-31 PEB 20570 PEB 20571 Application Hints 9.4 Reset Behaviour RESET DSP_FRQ External Clock CLK_DSP DELIC-LC/-PB Figure 98 Guaranteed Reset Behaviour If the DELIC DSP uses the internal 61.44 MHz clock, the reset value of the DELIC registers can only be guarantied 200 ns after the rising edge of the reset signal. If an external DSP clock is used, the reset behaviour is normal, e.g. the reset values are valid after the falling edge of the reset signal. In order to guaranty the reset behaviour of the DELIC in any case, the external circuity as shown in Figure 98 is recommended. During reset, the DSP is clocked externally. When reset is deactivated the internal DSP clock is used. Note: The frequency of the external clock is not important. The higher the frequency the faster the reset values are valid. A clock frequency in the range of several MHz (e.g. 4 MHz) is recommended. Data Sheet 287 2003-07-31 PEB 20570 PEB 20571 Glossary 10 AHV-SLIC PEB 4165 CMOS CO CODEC DC DECT DELIC DSL DSP HDLC IEEE INFO I/O IOM-2 IOM-2000 ISDN ITU P OCTAT-P LT-S LT-T PLL PBX AFE DFE QUAT-S SLICOFI-2 PEB 3265 Glossary High voltage part of SLIC Complementary Metal Oxide Semiconductor Central Office Coder Decoder Direct Current Digital European Cordless Telecommunication DSP Embedded Line and Port Interface Controller (PEB 20570, PEB 20571) Digital Subscriber Line Digital signal processor High-level Data Link Control Institute of Electrical and Electronic Engineers U- and S-interface signal as specified by ANSI/ETSI Input/Output ISDN-Oriented Modular 2nd generation Proprietary ISDN interface for S/T and UPN Integrated services Digital Network International Telecommunications Union Micro Processor OCTAl Transceiver for UPN-Interfaces (PEB 2096) Line Termination-Subscriber Line Termination-Trunk Phase-Locked Loop Private Branch Exchange 4-channel analog front end of U-transceiver (PEB24902) 4-channel digital front end of U-transceiver (PEB24911) QUAdrupleTransceiver for S/T-Interface (PEB 2084) Dual channel CODEC + low voltage part of SLIC Data Sheet 288 2003-07-31 PEB 20570 PEB 20571 Glossary SOCRATES S/T TAP SHDSL One Chip Rate Adaptive Transceiver with Embedded Start Up Two-wire pair ISDN interface Test Access Port Data Sheet 289 2003-07-31 PEB 20570 PEB 20571 Index 11 A Index T TRANSIU Initialization 71 Overview of Features 71 Applications 7 B Block Diagram 70 Block Diagram of the DELIC-LC 3, 125 Boot Strap Pin Setting 130 U UPN line interface Frame structure 76 D Differences DELIC-LC - DELIC-PB 69 V VIP Initialization 72 F Features DELIC-LC 4 DELIC-PB 4 I Interfaces IOM-2000 41 Overview 40 Interrupts 66 IOM-2000 Command and Status Interface 72 IOM-2000 Frame Structure 42 J JTAG Test Interface 67 L Logic Symbol 6 P Pin Definitions 12, 24 Pin Diagram 10 Principle Block Diagram of the DELIC-PB 3 S S/T State Machine 54 Strap Pin Definitions 38 Data Sheet 290 2003-07-31 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG |
Price & Availability of PEB20571
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |